Overflow prediction algorithm and logic for high speed...

Details Overflow prediction algorithm and logic for high speed... Overflow prediction algorithm and logic for high speed...

2005-09-20

2005-09-20

Mai, Tan V. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S552000

Reexamination Certificate

active

06947962

ABSTRACT:
An algorithm and implementation is described of overflow prediction for addition without the use of an expensive addition operation. This overflow prediction is particularly applicable to the implementation of addition operation using the carry-save format in high speed arithmetic units.

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H. Suzuki et al, “Leading Zero Anticipatory Logic for High Speed Floating Point Addition”, IEEE Journal of Solid-State Circuits, vol. 31, No. 8, Aug. 1996 pp. 1157-1164.
K.T. Lee and K.J. Nowka, “1Ghz Leading Zero Anticipator Using Independent Sign-Bit Determination Logic”, 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 194-195.
E. Hokenek et al, “Second Gemation RISC Floating Point with Multiply-Add Fused”, IEEE Journal on Solid-State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1207-1213.

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