Overflow detector for FIFO

Details Overflow detector for FIFO Overflow detector for FIFO

2001-01-29

2002-05-28

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Applications

Control

C377S026000, C377S028000, C365S221000

Reexamination Certificate

active

06396894

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to high-speed integrated circuits and more particularly to a method and circuitry for implementing overflow detection structures for high-speed first-in-first-out (FIFO) operations.
FIFOs are used in a variety of circuit applications. For example, a serializer may use a FIFO structure to address different system timing requirements. In such an application, the integrated circuit often employs an internal clock that may not be synchronized with an external clock used to supply data to the integrated circuit. A FIFO is used to transfer the data from the external clock regime to the internal clock regime. Typically, such a FIFO includes a number of registers that operate in response to a write pointer and a read pointer. An external clock controls the write pointer while an internal clock controls the read pointer. A problem arises when the read and write pointers collide, that is, when they attempt to read and write the same FIFO register at about the same time. This condition is commonly referred to as an overflow condition and can result from improper resetting of the FIFO pointers caused by, for example, glitches in the pointer generation circuits, drifting of the external clock phase, etc. During an overflow condition, the data read from the FIFO may be corrupted. FIFOs thus need some type of overflow detection mechanism to detect an overflow condition and avoid this faulty operation.
Conventionally, overflow detection has been implemented using combinatorial logic whereby the read and write pointers into the same FIFO register are gated together to flag an overflow signal. Specifically, the read and write signals are logically ANDed such that when a collision occurs, an overflow detection signal is asserted. These types of overflow detection suffer, however, from possible glitches and thus erroneous flagging of overflow. Data loss occurs when an overflow detector output is used to reset the FIFO and to separate the read and write pointers. While a FIFO register resets, it cannot accept new data. Thus, an erroneous overflow flagging can cause data loss.
There is thus a need for an improved method and circuitry for implementing high-speed FIFO and overflow detection structures.
SUMMARY OF THE INVENTION
The present invention provides method and circuitry for implementing high speed FIFO structures with improved overflow detection mechanism. In one embodiment read pointes are recorded into registers that are clocked by their corresponding write pointers. The outputs of the registers are then logically combined to generate a signal indicating an overflow condition. By making the duty cycle of the write clock signals smaller than the duty cycle of the read signals, proper detection of an overflow condition is guaranteed.
Accordingly, in one embodiment, the present invention provides a FIFO that includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock input of one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The FIFO further including an overflow detector having a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.
In a specific embodiment, outputs of the plurality of clocked registers logically combine at an OR gate. In another embodiment, the write clock duty cycle for the write pointer is smaller than the read clock duty cycle for the read pointer.
In another embodiment, the overflow detector incudes a clock present signal for detecting when the write clock stops toggling. The overflow detector generates an overflow detection signal when the clock present signal is not asserted.
In yet another embodiment, the present invention provides a method for detecting overflow in a FIFO structure that uses read pointers and corresponding write pointers, the method including recording each read pointer into a register clocked by its corresponding write pointer; and logically combining outputs of all registers. The method further reducing a duty cycle of the write pointers compared to the duty cycle of the read pointers.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the FIFO with the overflow detection according to the present invention.


REFERENCES:
patent: 4873667 (1989-10-01), Geadah et al.
patent: 6101329 (2000-08-01), Graef
patent: 6172927 (2001-01-01), Taylor

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