Overflow detector for algebraic adders

Details Overflow detector for algebraic adders Overflow detector for algebraic adders

1983-01-28

1986-05-27

Thomas, James D.

Boots, shoes, and leggings

364737, G05F 750

Patent

active

045920087

ABSTRACT:
An MOS high-speed overflow detector for algebraic adders which add two binary numbers (a,b) in two's complement notation and contain one full adder per digit which provides a sum signal (s) and a carry signal (c) consists of a complex gate (k) made up of three two-input AND elements (u1, u2, u3). The outputs of the three AND elements are NORed. The two inputs of the first AND element (u1) are fed with the sign signal (va) of the first binary number (a) and with the inverted sign signal (vb) of the second binary number (b), respectively. The two inputs of the second AND element (U2) are fed with the sign signal (vb) of the second binary number (b) and with the sum signal (vs) of the full adder (av) of the sign digit, respectively. The two inputs of the third AND element (u3) are fed with the inverted sum signal (vs) and the inverted sign signal (va) of the first binary number (a), respectively.

REFERENCES:
patent: 3016193 (1962-01-01), Brett et al.
patent: 3720821 (1973-03-01), Heightley
patent: 3789206 (1974-01-01), Heightley
patent: 4215415 (1980-07-01), Kanemasa et al.
patent: 4223389 (1980-09-01), Amada et al.
patent: 4282581 (1981-08-01), Bondurant et al.

Affiliated with

Also associated with

Rating

Overflow detector for algebraic adders does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Overflow detector for algebraic adders, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Overflow detector for algebraic adders will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1574897