Overflow detection system and its circuit for use in addition an

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364737, G06F 738, G06F 1100

Patent

active

052608905

ABSTRACT:
In an overflow detection circuit for A+B operation, an inverter outputs a value V.sub.B ' comprising inverted bits of a numeric part of an addend B. A comparator receives as an input a numeric part V.sub.A of an augend A and an output V.sub.B ' of the inverter, and responsive thereto outputs a signal C indicating whether or not V.sub.A >V.sub.B ' is given. Sign parts S.sub.A and S.sub.B of A and B and the output C of the comparator are inputted into the a decoder and an overflow signal "0" is outputted. The decoder is a circuit which outputs "1" when S.sub.A and S.sub.B are "0" and V.sub.A (V.sub.A >V.sub.B ') is large and when S.sub.A and S.sub.B are "1" and V.sub.A is small (VA=V.sub.B '), and output "0" in other cases. If the comparator is a circuit for determining V.sub.A .gtoreq.V.sub.B ', the overflow of A+B+1 can be detected. Thus, the overflow of the result of operation can be detected earlier than an adder and a substracter output the results.

REFERENCES:
patent: 4379338 (1983-04-01), Nishitani et al.
patent: 4706209 (1987-11-01), Picco
patent: 4768160 (1988-08-01), Yokoyama
patent: 4941119 (1990-07-01), Moline

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