Overflow detection for integer-multiply instruction

Details Overflow detection for integer-multiply instruction Overflow detection for integer-multiply instruction

1996-02-26

1998-09-01

Ngo, Chuong D.

Boots, shoes, and leggings

G06F 738

Patent

active

058019782

ABSTRACT:
An arithmetic logic unit includes overflow trap logic for an integer-multiply instruction. A multiply unit multiplies a pair of n-bit operands together and produces a n+1 bit result. The low order n-bits are returned as the multiplication result. A first overflow logic unit examines the leading bits of both operands and counts the number of leading bits which are equal to respective sign bits. If the count is smaller than n, an overflow trap is signalled. If not, then a second logic unit examines bits n and n-1 of the result and signals an overflow trap if these bits are not equal.

REFERENCES:
patent: 4575812 (1986-03-01), Kloker et al.
patent: 4941119 (1990-07-01), Moline
patent: 5138570 (1992-08-01), Argade
patent: 5422805 (1995-06-01), McIntyre et al.

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