Overflow and underflow processing circuit of a binary adder

Details Overflow and underflow processing circuit of a binary adder Overflow and underflow processing circuit of a binary adder

1994-10-18

1997-10-14

Ngo, Chuong D.

Boots, shoes, and leggings

364737, G06F 738, G06F 1100

Patent

active

056778600

ABSTRACT:
Two input data X (7), Y (7), . . . , X (0), Y (0) are input to a plurality of full adders, and an overflow/underflow signal of each full adder is input to a full adder of a higher level. An overflow/underflow signal Co of the full adder of the most significant bit and data Y (7) are applied to an EXOR gate to obtain an exclusive OR. According to an output signal of the EXOR gate, an added output of each full adder or data Y (7) is selected by a selector, whereby a straight binary signal is output.

REFERENCES:
patent: 4706209 (1987-11-01), Picco
patent: 4722066 (1988-01-01), Armer et al.
patent: 4768160 (1988-08-01), Yokoyama
patent: 4819198 (1989-04-01), Noll et al.
patent: 5289396 (1994-02-01), Taniguchi
patent: 5448509 (1995-09-01), Lee et al.

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