Over-sampling type clock recovery circuit with power consumption

Details Over-sampling type clock recovery circuit with power consumption Over-sampling type clock recovery circuit with power consumption

1999-03-12

2000-10-10

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331DIG2, 375376, 327149, H03L 700

Patent

active

061305847

ABSTRACT:
An over-sampling type clock recovery circuit includes a phase difference detecting section, a phase adjusting section and a signal selecting section. The phase difference detecting section detects a phase difference between a data signal and each of a plurality of active sets of clock signals, and generates a phase adjustment signal from a plurality of phase difference data corresponding to the detected phase differences using a majority determination. The phase adjusting section generates N (N is an integer equal to or larger than 2) sets of clock signals and adjusts phases of clock signals of the N sets based on the phase adjustment signal. The signal selecting section selects a part or all of the N sets of clock signals based on the detected phase differences from the phase difference detecting section. The selected sets of clock signals are supplied to the phase difference detecting section as the plurality of active sets of clock signals.

REFERENCES:
patent: 5633899 (1997-05-01), Fiedler et al.
Lee, et al.; "A 622Mb/s/CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array".

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