Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator
Patent
1999-03-12
2000-09-26
Pascal, Robert
Oscillators
Automatic frequency stabilization using a phase or frequency...
Plural a.f.s. for a single oscillator
331DIG2, 327149, 375376, H03L 700
Patent
active
061247626
ABSTRACT:
An over-sampling type clock recovery circuit includes a phase difference detecting section (TIPD, CP, LFP), a phase adjusting section (VCO, VD, FD) and a signal selecting section (LDEC, SW). The phase difference detecting section (TIPD, CP, LFP) detects a phase difference between a data signal and each of a plurality of active sets of clock signals, and generates a phase adjustment signal from a plurality of phase difference data corresponding to the detected phase differences. The phase adjusting section (VCO, VD, FD) generates N (N is an integer equal to or larger than 2) sets of clock signals and adjusts phases of clock signals of the N sets based on the phase adjustment signal. The signal selecting section (LDEC, SW) selects a part or all of the N sets of clock signals based on the detected phase differences from the phase difference detecting section. The selected sets of clock signals are supplied to the phase difference detecting section as the plurality of active sets of clock signals.
REFERENCES:
Lee, et al., "A 622Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array", in IEEE International Solid-State Circuit Conference Digest of Technical Papers, PP. 198-199, 1996.
Glenn Kimberly E.
NEC Corporation
Pascal Robert
LandOfFree
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