Over-sampling type clock recovery circuit using majority...

Details Over-sampling type clock recovery circuit using majority... Over-sampling type clock recovery circuit using majority...

1999-03-12

2001-04-24

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331SDIG002, C375S376000, C327S149000

Reexamination Certificate

active

06222419

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a clock recovery circuit in which clock signals are extracted from an inputted data signal, and more particularly, to an over-sampling type clock recovery circuit which performs sampling with a plurality of clock signals having different phases.
2. Description of the Related Art
In recent years, a high-speed protocol is proposed, such as Gbit Ethernet and Fiber Channel for data transmission. For this purpose, high speed processing is requested to a clock recovery circuit which extracts a clock signal from a data signal in a high speed transmission and a PLL circuit which establishes frequency synchronization between an internal clock signal and the transmitted clock signal. In order to respond to such a request, as disclosed in 1996 IEEE International Solid-State Circuits Conference, an over-sampling-type clock recovery circuit is proposed in which a transmitted data signal is sampled with a plurality of clock signals with different phases generated by an internal circuit.
FIG. 1
shows a block diagram of a clock recovery circuit which is disclosed in the conventional example. A data signal is supplied to eight phase comparators TIPD
0
to TIPD
7
. Each phase comparator TIPD is supplied with every three clock signals of 24 clock signals having fixed delays outputted from a fixed delay circuit FD and detects a phase state between the data signal supplied and three clock signals.
When the data signal is delayed more in relation to the clock signals, the phase comparator TIPD detects the leading of the clock signal in phase to set a dn signal as an output of the circuit to an enable state and an up signal as another output of the circuit to a disable state. Similarly, when detecting the delay of the clock signals in phase, the phase comparator TIPD sets the up signal to the enable state and the dn signal to the disable state.
FIGS. 2A
to
2
F show a locking state. In this case, there is no delay or leading the clock signals in phase as shown in
FIGS. 2A
to
2
D. Therefore, both of the up signal and the dn signal are set to the disable state, as shown in
FIGS. 2E and 2F
. On the other hand,
FIGS. 3A
to
3
D shows the delay state of the clock signals. At this time, the up signal is set to the enable state, as shown in FIG.
3
E and the dn signal is set to the disable state, as shown in FIG.
3
F. In case of the leading state of the clock signals, the up signal is set to the disable state, and the dn signal is set to the enable state.
Each of charge pumps CP
0
to CP
7
increases the output voltages when the up signal is set to the enable state and decreases the output voltage when the dn signal is set to the enable state. A low pass filter LPF inputs the output voltages from the charge pumps CP
0
to CP
7
and integrates the change of these voltages. A variable delay circuit VD is supplied with the output voltage of the low pass filter LPF and a reference clock signal which is the output of a voltage controlled oscillator VCO. The variable delay circuit VD delays the reference clock signal in accordance with the output voltage from the low pass filter LPF. The fixed delay circuit FD is supplied with the output of the variable delay circuit FD and generates the 24 clock signals having fixed delays from the supplied clock signal.
In this way, in the conventional clock recovery circuit, each of the eight phase comparators TIPD
0
to TIPD
7
detects the leading or delay state of the clock signals in phase to set the up signal or dn signal is set to the enable state. As a result, the voltage outputted from the corresponding charge pump CP increases or decreases. Therefore, the variable delay circuit VD delays the reference clock signal based on the output voltage from the low pass filter LPF. The fixed delay circuit FD generates the 24 clock signals from the delayed reference signal. As a result, the phase leading or delay state of the clock signals in each of the phase comparators TIPD
0
to TIPD
7
is set to an adequate state so that the appropriate sampling of the data signal can be realized.
However, in the conventional clock recovery circuit, there is a problem. That is, the data sampling cannot be correctly performed when the phase differences are generated between the 24 clock signals due to the influence of a layout of wiring patterns in the clock recovery circuit. Especially, the data sampling cannot be correctly performed when the phase differences are generated between three clock signals supplied to the phase comparator TIPD. For example, when the a phase shift (delay) of the clock signal is generated in one of the three clock signals as shown in
FIG. 3D
, the phase comparator TIPD detects a clock delay state so that the up signal is set to the enable state. For this reason, the charge pump CP receives the up signal of the enable state and the fixed delay circuit FD delays the 24 clock signals. As a result, a correct data sampling cannot be performed in the whole clock recovery circuit including other phase comparators TIPD.
In addition to the above conventional example, a digital signal receiving apparatus is disclosed in Japanese Laid Open Patent application (JP-A-Showa 61-
145945).
In this reference, the digital signal receiving apparatus is composed of a reproducing section and a majority determining section and a conversion section. The reproducing section reproduces clock signals having a basic clock signal frequency fr and a frequency n (n is a positive integer equal to or larger then 3) times of the basic clock signal frequency fr locked to a digital reproduction signal in phase. The majority determining section extracts n samples values during one bit of the digital reproduction signal based on nfr clock signals, and determines binary values of the n sample values on the majority side as a value during the bit. The converting section converts the determined value to have 1/fr width. Thus, the digital reproduction signal is shaped in units of basic clocks fr of the digital reproduction signal.
Also, a data sampling converting circuit is disclosed in Japanese Laid Open Patent application (JP-A-Showa 61-
214842).
In this reference, the data sampling converting circuit is composed of a clock reproducing circuit, a frequency dividing circuit and a determining circuit. The clock reproducing circuit reproduces a clock pulse from a character multiplexed signal. The frequency dividing circuit divides the reproduced clock signal in frequency to 1 to n-th, and generates n sampling pulses with different phases. The determining circuit performs sampling of the character multiplexed signal with the n sampling pulses and determines based on majority determination of m continuous sampling results whether a digital data is in a high level or a low level.
Also, a demodulation data identifying and determining apparatus is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 3-69238). In this reference, the demodulation data identifying and determining apparatus is composed of a detecting and demodulating circuit, a comparator, a clock reproducing circuit, a timing determining section, a latch circuit. The detecting and demodulating circuit demodulate an input signal to output a base band signal. The comparator converts the base band signal into a binary signal. The clock reproducing circuit reproduces a reproduction clock signal having the same frequency as a bit rate of a transmission data, and generates a clock signal faster than the reproduction clock signal. The timing determining section performs sampling of the binary signal using the clock signal and performs majority determination to a plurality of values corresponding to a plurality of sampling points to output the result of the majority determination. The latch circuit latches the output from the timing determining section in accordance with the reproduction clock signal to output as a reproduced digital data.
Also, a digital signal reproducing circuit is disclosed in Japanese Laid Open Patent application (JP-A-Heisei

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