Output state protection network for D-type flip-flop

Details Output state protection network for D-type flip-flop Output state protection network for D-type flip-flop

1985-10-11

1988-01-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307458, 307542, 307546, 307443, H03K 3289, H03K 329

Patent

active

047193662

ABSTRACT:
A D-type master-slave flip-flop includes a master section, a slave section and an output state protection network. The master section has a data input node and a clock input node. The slave section has at least one data output node connected to an output terminal. The output state protection network is responsive to the master section for toggling the slave section so that the data output node is returned to its initial logic state when the output terminal is free of transient noise.

REFERENCES:
patent: 4517475 (1985-05-01), Petty
Eardley, "Latch Circuit Insensitive to Disturbance by Alpha Particles," IBM Tech. Disclosure, vol. 24, No. 12, May 1982, pp. 6461-6462.

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