Output stage synchronization

Details Output stage synchronization Output stage synchronization

2004-03-19

2008-10-14

Wang, Ted (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S354000, C375S357000, C375S359000, C375S372000

Reexamination Certificate

active

07436918

ABSTRACT:
Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock domains. One embodiment of the invention comprises a mechanism for passing data from a first clock to a second clock domain in a digital pulse width modulated (PWM) amplification system. In this embodiment, parallel data is generated in the process of converting PCM data to PWM data. The parallel data is processed in a clock domain having a first clock rate and is passed to a second clock domain having a clock rate that is twice the rate of the first clock domain. The parallel data is then serialized at the higher clock rate of the second clock domain.

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patent: 2200817 (1988-08-01), None

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