Amplifiers – With semiconductor amplifying device – Including push-pull amplifier
Reexamination Certificate
1999-12-13
2001-09-18
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including push-pull amplifier
C330S274000
Reexamination Certificate
active
06292057
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of operational amplifiers; and, in particular, to an output stage and method having a latchup-free sourcing current booster capable of driving low impedance loads.
BACKGROUND OF THE INVENTION
Well known in monolithic integrated circuit design, the design of bias circuitry internal to the chip is very critical since it determines the internal voltage and current levels over all operating conditions of the integrated circuit as well as over all manufacturing process variations. The industry trend for electronic systems encompassing operational amplifiers is evolving toward lower operating voltages supplied from battery sources. Thus, amplifiers are used in applications requiring low voltage single supply operations in addition to traditionally desired operational amplifier properties such as high input impedance, low input offset voltage, low noise, high bandwidth, high speed and sufficient output drive capabilities. The operational amplifier consists of at least two stages: an input amplifier stage and an output stage. The input amplifier stage has the task of deriving the difference between the two inputs. The primary purpose of the output stage is voltage amplification. The output stage optionally has some sort of current boosting scheme which increases the amplifier's load capacity. Conventionally, amplifier output stages have used techniques involving combinations of transistors including npn, pnp and metal oxide semiconductor field effect transistors to satisfy many performance specifications, such as low crossover distortion, large output voltage swings including rail to rail performance, excellent phase and gain margins, low output impedance and symmetrical source and sink capabilities. A well-designed output stage should achieve these performance specifications while consuming low quiescent power and not limiting the frequency response of the amplifier.
During operation, an amplifier circuit consumes current from a power supply. A portion of this current, known as the quiescent current, is used to bias the internal circuitry of the amplifier. A low quiescent current is desirable because it reduces power consumption when the amplifier is operating at a light load, or with no load at all.
FIG. 1
illustrates a conventional output stage
10
. This circuit schematic illustrates an embodiment of a traditional Class AB output stage
10
of an operational amplifier capable of driving a specified minimum impedance load while possessing a low quiescent current. Current source
12
provides quiescent biasing current I
Q
to drive the base of sourcing transistor
26
. Sinking transistor
30
coupled in series with sourcing transistor
26
sinks current from the external load provided at output node
28
. Current mirror transistor
22
has its base and emitter coupled to the base and emitter of the sinking transistor
30
, respectively. In addition, the base of current mirror transistor
22
is coupled to input
16
. Diode
14
is coupled in series between the collector of current mirror transistor
22
and the current source
12
. The resistor
18
is coupled between the diode
14
and the output terminal of output stage
28
. Diode
20
is coupled in parallel with resistor
18
to provide diode-resistor current limiting. Raising the quiescent current will drive lower impedance loads. This type of design modification, however, leads to too much standby power dissipation and; thus, is inefficient.
As is illustrated in
FIG. 2
a
, another amplifier design
40
uses a simple boosting scheme to generate higher output current I
out
through the use of positive feedback. A current mirror circuit
44
formed by transistors
46
and
48
provides a boosting current I
boost
from the biasing current source
58
to drive the base of an sourcing transistor
52
. The emitters of both current mirror transistors
46
and
48
are coupled to a first power supply rail
42
having power V
CC
. The bases of both current mirror transistors
46
and
48
are tied together. Accordingly, the current mirror transistor
48
has a directly coupled base and collector. Resistor
50
has small resistance R coupled in parallel to the current mirror circuit
44
such that when the current of sourcing transistor
52
is small, the resistor
50
does not have any significant voltage drop across it. Current source
58
is coupled to the current mirror circuit
44
supplies a bias current I
bias
to drive the current mirror circuit
44
. Current I
boost
provided by the current mirror
44
through current mirror transistor
46
drives the sourcing transistor
52
. Boosting current I
boost
approximately equals the bias current I
bias
. Current I
out
flows through sourcing transistor
52
to an output node
56
. Sinking transistor
54
coupled in series with sourcing transistor
52
sinks current from the external load provided at output
56
. Sinking transistor
54
is coupled to a input amplifier (not shown) at input node
60
. As the current in sourcing transistor
52
increases, the voltage drop across resistor
50
increases. The current in first current mirror transistor
46
increases exponentially with the voltage increase across resistor
50
. Thus, current in first current mirror transistor
46
grows exponentially as the current in sourcing transistor
52
increases linearly, making the boosting current I
boost
in current mirror circuit
44
non-linear. Once boosting current I
boost
has reached a level too high for sourcing transistor
52
, transistor
52
will conduct heavily, raising the output to the power supply voltage level and causing the circuit to latch-up. Thus, the circuit ceases operation due to latch-up at higher output currents. Decreasing the value of resistance
50
in an effort to prevent the occurrence of latch-up, results in decreased boosting current I
boost
, which defeats the purpose of providing a current boosting scheme. In conclusion, a limitation of this particular type of topology exists such that it may be used solely with external loads having a specified limited range. This limitation exists primarily because the biasing signal of this boosting scheme has no dependence upon the input signal; yet, biases the output stage
40
based upon its output signal.
FIG. 2
b
illustrates another conventional amplifier design
70
which uses another boosting scheme to generate higher output current I
out
. This amplifier
70
includes an output driver having a sourcing transistor
78
coupled to sinking transistor
80
at a common output node
82
. Transistor
76
includes a base coupled to the input signal
74
, an emitter coupled to a first power supply reference
72
and a collector coupled to the base of the sourcing transistor
78
. Current through transistor
76
provides ample boosting current I
boost
for the base of sourcing transistor
78
. Accordingly, this design provides boosting current that is based upon both the input signal and the output signal of the amplifier and, thus, is capable of sourcing a large output current. The limitation of this design, however, is the existence of a low power supply rejection ratio.
Hence, a need exists for a versatile operational amplifier that can be used in a variety of applications, especially low voltage applications that does not diminish the characteristics of the operational amplifier. A need exists for an output stage that provides a variable quiescent current relative to the impedance load without the occurrence of latchup and high output voltage swing. A need exists for an output stage having an energy efficient design for low impedance loads and a stable negative feedback architecture that is linearly controlled.
SUMMARY OF THE INVENTION
An output stage of an operational amplifier having a sourcing current boosting scheme in accordance with the present invention generates a variable bias current and is capable of driving low impedance loads, while preventing the latch-up phenomenon. Through the use of a self-adjusting current boosting circuit, the bias
Corsi Marco
Escobar-Bowser Priscilla
Brady W. James
Mosby April M.
Nguyen Khanh Van
Pascal Robert
Telecky , Jr. Frederick J.
LandOfFree
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