Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2000-02-18
2001-07-31
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
Reexamination Certificate
active
06268762
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an output stage for a charge pump and more particularly to a charge pump with such an output stage having minimal voltage swings due to the output loading.
BACKGROUND OF THE INVENTION
Charge pumps are well known in the art. Charge pumps are electrical circuits which receive a low voltage as an input and generate a high voltage as an output. Charge pumps are used in non-volatile memory arrays to generate the necessary high voltage for erase or programming operations.
Referring to
FIG. 1
there is shown a block level diagram of a charge pump
10
of the prior art. A typical charge pump
10
of the prior art comprises a first stage
12
for receiving the input voltage Vcc and for generating an output voltage which is supplied to a plurality of serially connected alternating pumps
20
a
and
20
b
. Thus, the output of the initial stage
12
is supplied as an input to a first stage
20
a
to which clock signal C
1
and C
2
A are supplied. The output of the first pump stage
20
a
is supplied as an input to the second pump stage
20
b
to which clock signals C
2
and C
1
A are supplied. The output of the second pump stage
20
b
is then supplied as input to yet another serially connected first pump stage
20
a
and so on. The last stage
16
of the charge pump
10
is either the charge pump
20
a
or
20
b
with the output as the output of charge pump
10
.
Referring to
FIG. 2
, there is shown a detailed circuit diagram of the initial stage
12
of the charge pump
10
of the prior art. The initial stage
12
simply comprises an NMOS transistor having its gate connected to one of the terminals to the input voltage Vcc. The output of the initial stage is the second terminal of the NMOS transistor.
Referring to
FIGS. 3 and 4
, there is shown a detailed circuit diagram of the charge pump stages
20
a
and
20
b
. Each of the pump stages
20
a
and
20
b
are identical in circuit. The only difference between the stages
20
a
and
20
b
is the clock signals supplied thereto. Thus, as shown in
FIG. 3
, the charge pump stage
20
a
comprises an NMOS transistor
22
a
having a first terminal and a second terminal with a channel therebetween. A gate controls the flow of current between the first terminal and the second terminal. The first terminal of the NMOS transistor
22
a
is connected to the input. A second NMOS transistor
24
a
also comprises a first terminal and a second terminal with a channel therebetween. A gate controls the flow of current between the first terminal and the second terminal. The first terminal of the second NMOS transistor
24
a
is also connected to the input. The second terminal of the first NMOS transistor
22
a
is connected to the gate of the second NMOS transistor
24
a
. The second terminal of the second NMOS transistor
24
a
is connected to the output. The charge pump stage
20
a
also comprises a third NMOS transistor
26
a
having its first and second terminals connected together to receive the clock signal C
1
. The gate of the third NMOS transistor
26
a
is connected to the output and to the gate of the first NMOS transistor
22
a
. Finally, the first pump stage
20
a
also comprises a fourth NMOS transistor
28
a
. The first and second terminals of the fourth NMOS transistor
28
a are connected together and receive the clock signal C
2
A. The gate of the fourth NMOS transistor
28
a
is connected to the gate of the second NMOS transistor
24
a.
In like manner, the second pump stage
20
b
comprises a first, a second, a third, and a fourth NMOS transistors
22
b
,
24
b
,
26
b
, and
28
b
, respectively, and all as connected in the manner for the first charge pump stage
20
a
, shown in FIG.
3
. As previously discussed, the only difference between the second charge pump stage
20
b
and the first charge pump stage
20
a
is the clock signal. In the second charge pump stage
20
b
, clock signal C
2
is supplied to the first and second terminal of third NMOS
26
b
. A clock signal C
1
A is supplied to the first and second terminals of the fourth NMOS transistor
28
b.
The charge pump
10
of the prior art receives two clock signals C
1
, C
2
, C
1
A, C
2
A whose waveforms are shown in FIG.
5
.
The problem with the charge pump
10
of the prior art is that with either the first pump stage
20
a
or the second stage
20
b
as the last stage
16
of the charge pump
10
, the voltage output of the charge pump
10
with a load has a swing in the voltage output, as shown in FIG.
6
.
SUMMARY OF THE INVENTION
In the present invention, an output stage for a two-clock charge pump receives a first signal as an input. A first MOS transistor has a first terminal and a second terminal with a channel therebetween and a gate to control the flow of the current therebetween. A second NMOS transistor has a first terminal and a second terminal with a channel therebetween and a gate to control the flow of the current therebetween A first diode means has a first terminal and a second terminal. A second diode means has a first terminal and a second terminal. The first terminal of the first MOS transistor is connected to the first terminal of the second MOS transistor and is connected to the input to receive the first signal. The gate of the first MOS transistor is connected to the first terminal of the first diode means and to the second terminal of the second diode means and receives a first clock signal. The second terminal of the first MOS transistor is connected to the gate of the second MOS transistor and receives a second clock signal. The second terminal of the second MOS transistor is connected to the second terminal of the first diode means and to the first terminal of the second diode means and supplies an output signal of the output stage.
The present invention also relates to a charge pump having the foregoing output stage.
REFERENCES:
patent: 5734290 (1998-03-01), Chang et al.
patent: 5818289 (1998-10-01), Chevallier et al.
patent: 6016073 (2000-01-01), Ghilardelli et al.
patent: 6172886 (2001-01-01), Lauterbach et al.
Gray Cary Ware & Friedenrich LLP
Silicon Storage Technology, Inc.
Zweizig Jeffrey
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