Output stage ESD protection for an integrated circuit

Details Output stage ESD protection for an integrated circuit Output stage ESD protection for an integrated circuit

2000-07-26

2003-03-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C361S090000, C361S091100, C327S327000, C327S314000

Reexamination Certificate

active

06529059

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to integrated circuits, and in particular to electrostatic discharge protection (ESD) of circuitry coupled to an output stage of an integrated circuit.
BACKGROUND OF THE INVENTION
The protection of integrated circuits (ICS) from damage due to ESD has received increased design attention, particularly as circuit geometries migrate to smaller dimensions. ESD damage can occur as a result of a voltage ESD event or a current ESD event. The book “ESD in Silicon Integrated Circuits” by A. Amerasekera and C. Duvvury, copyrighted in 1995 by John Wiley & Sons, which is hereby incorporated by reference, discloses much about the topic of electrostatic discharge phenomena. The damage may occur during manufacture of the IC chip, or more commonly, after the chip is packaged such as during handling, shipping or use.
One ESD protection technique to protect the input of a packaged IC employs resistors to reduce ESD voltages transmitted to the IC through bond pads. ESD events are transmitted to chip bond pads of packaged chips by package leads. Another technique employs a transistor to clamp the operating voltage on an input bond pad to a safe level. Yet another technique employs a four-layer device, such as a thyristor, to introduce hysteresis into the protective circuitry. Yet another technique protects the input of an integrated circuit from an ESD event has been to provide two steering diodes, each having an area large enough to conduct the expected current
Another prior art technique, shown in
FIG. 8
, has a first steering diode
30
h
between the output bond pad
14
h
and the positive supply bond pad
28
h
. The first steering diode has a cathode coupled to the positive supply bond pad and an anode coupled to the output bond pad. The first steering diode is reverse-biased and non-conducting under normal operating conditions. The first steering diode provides a low impedance path from the output bond pad to the positive supply bond pad
28
h
when the output bond pad voltage is more than one diode voltage drop above the voltage at the positive supply bond pad. The second steering diode
32
h
is coupled between the ground bond pad
18
h
and the output bond pad
14
h
. The second steering diode has a cathode coupled to the output bond pad and an anode coupled to the ground bond pad. The second steering diode under normal operating conditions is reverse-biased and non-conducting. The second steering diode provides a low impedance path from the output bond pad to the ground bond pad in the event the output bond pad voltage is more than one diode voltage drop below the voltage at the ground bond pad. The first and second steering diodes are sized to accommodate the largest current expected due to an ESD event.
In radio frequency circuits, the output bond pad is typically inductively coupled to the positive supply. The DC bias voltage on the collector is almost equal to the positive supply voltage, therefore any positive going signal will cause the output voltage at the output bond pad to exceed the DC supply voltage. When the normal output voltage swing exceeds one diode voltage drop, the first steering diode
30
h
conducts and limits the output voltage, undesirably distorting the radio frequency signal.
While such techniques have offered some ESD protection, further improvement is considered necessary. The need for a new ESD protection technique for circuits coupled to an output stage is desirable.
SUMMARY OF THE INVENTION
In accordance with the present invention, an integrated circuit includes a circuit coupled between an output bond pad and a ground bond pad. The circuit includes a transistor having a first electrode coupled to the output bond pad and a second electrode coupled to the ground bond pad. A degeneration device is coupled between the second electrode and the ground bond pad. At least one diode is coupled between the second electrode and the ground bond pad with the anode of the at least one diode coupled to the second electrode and the cathode of the at least one diode coupled to the ground bond pad.


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“Input-protection scheme tops other approaches”, Mediatronix Private Limited, Kerala, India, Kannan Natarajan, EDN Jan. 6, 2000. P. 124.
“Input-Protection Scheme Tops Other Approaches,” K. Natarajan, Mediatronix Private Limited, Kerala, India,Design Ideas, EDN, Jan. 6, 2000.
“ESD In Silicon Integrated Circuits,” Ajith Amerasekera et al.,Design And Measurement in Electronic Engineering, 1995.

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