Output stage and method of enhancing output gain

Details Output stage and method of enhancing output gain Output stage and method of enhancing output gain

2001-03-02

2003-07-01

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including push-pull amplifier

C330S263000

Reexamination Certificate

active

06586998

ABSTRACT:

FIELD
This invention pertains to an output stage, and more particularly to an output stage and method for preventing offset voltage error and improving output stability and performance.
BACKGROUND
It is known in the prior art to provide some degree of output stage control for amplifier outputs. However, prior art amplifier output stages have several limiting features which affect the amplification of the amplifier input signal and fail to provide adequate control of the amplifier output.
FIG. 1
depicts an example of a prior art amplifier
120
with an output stage
122
. One of the problems with prior art amplifier output stages is that they cause an excessively large reflection current (&Dgr;I) to be reflected back into amplifier
120
. The current reflection &Dgr;I will be reflected back through transconductance amplifier
120
and produce a systematic input offset error voltage (V
OS
) which can have significant effects on the performance of amplifier
120
. The resulting offset error voltage V
OS
is equivalent to the reflection current &Dgr;I divided by the amplifier transconductance (g
m
), V
OS
=&Dgr;I/g
m
. Therefore, any increase in &Dgr;I will result in an unwanted increase in offset error voltage V
OS
.
In the prior art amplifier output stage
122
, current I
o
provides the driving current to the base of a source NPN transistor Q
3
which in turn controls the current flow through transistor Q
3
and thus output voltage V
out
. Because the base current I
B
of a transistor provides control for the collector current I
C
through the known beta factor relationship of I
C
=I
B
*&bgr;, I
B3
provides control for the collector current I
C3
of transistor Q
3
and thus the output voltage V
out
. Therefore, to achieve a sufficiently large output voltage, V
out
, through transistor Q
3
, base current I
B3
of transistor Q
3
must be sufficiently large to drive I
C3
. To achieve a sufficiently large I
B3
, the base current of transistor Q
1
(I
B1
) must be sufficiently large (again, I
C
=I
B
*&bgr;) to generate a sufficiently large I
o
current to drive transistor Q
3
.
This large base current I
B1
causes a significant increase in the current at node N
1
. This increase at node N
1
results in an increase in reflection current &Dgr;I. The resulting increased &Dgr;I is reflected back through transconductance amplifier
120
resulting in an increased offset error voltage V
OS
which in turn affects the overall amplifier output voltage V
out
, depending on the closed-loop gain.
A similar analysis can be made with regard to driving transistor Q
2
which drives sink output transistor Q
4
. To achieve a sufficiently large output current through transistor Q
4
, a base current (I
B4
) of transistor Q
4
must be sufficiently large to produce a sufficiently large collector current (I
C4
) for transistor Q
4
. Therefore, I
o
through driving transistor Q
2
must be sufficient to drive sink output transistor Q
4
. This requires an increase in base current (I
B2
) for transistor Q
2
which in turn affects the current at node N
1
.
The prior art output stage
122
further affects the overall amplifier output voltage V
out
because of the needed implementation of Q
1
as a fast PNP transistor. To achieve a desired bandwidth and efficiency, Q
1
needs to be a fast transistor. Therefore, the Q
1
transistor is implemented with a vertical PNP configuration to improve response time. However, fast, vertical PNP transistors have a reduced &bgr;, which in turn reduces the driving current I
o
. Thus, to maintain I
o
at a sufficiently large level to drive source transistor Q
3
, I
B1
must be further increased. The further increase to I
B1
causes an increase in the current at node N
1
, resulting in an increase in reflection current &Dgr;I and thus an increase in offset error voltage V
OS
.
What is needed is an amplifier output stage which provides a sufficiently large driving current to the base of a source transistor without adversely increasing the reflection current &Dgr;I. What is further needed is an output stage which will significantly reduce or eliminate any reflection current &Dgr;I, where &Dgr;I is due to a mismatch of beta factors of NPN transistors (&bgr;
npn
) and PNP transistors (&bgr;
pnp
).
SUMMARY
The present invention provides for an output stage which couples with an input stage and is configured to limit a reflection current which is reflected back through the input stage producing an offset error input voltage affecting the performance of the input stage. The present output stage limits the reflection current by compensating for at least one bias current at the input stage output. The output stage further reduces a quiescent current needed to maintain the output stage in an active state without adversely affecting the output voltage supplied to the load. The output stage includes a first and second current driving stage, a first and second current compensation circuit and an output circuit. The first and second current driving stages couple with both the input stage and the output circuit. The first current driving stage is configured to generate a first driving current to drive the output circuit, wherein the first driving current is proportional to a first bias current based on an output from the input stage. The second driving stage is configured to generate a second driving current to also drive the output circuit, wherein the second driving current is proportional to a second bias current based on the output of the input stage. To limit reflection current back into the input stage, the first current compensation circuit couples with the first driving stage and the input stage, and is configured to compensate for the first bias current. To further limit the reflection current back into the input stage, the second current compensation circuit couples with the second driving stage and the input stage, and is configured to compensate for the second bias current.
In one embodiment, the first current driving stage further includes a first current multiplier coupled with the output circuit, and is configured to drive the output circuit at a sufficient level while limiting the first bias current. The second current driving stage further includes a second current multiplier coupled with the output circuit, and is configured to drive the output circuit at a defined level while limiting the second bias current. The first current compensation circuit includes a first current mirror coupled with the first current driving stage to compensate for the first bias current and the second current compensation circuit includes a second current mirror coupled with the second current driving stage to compensate for the first bias current. The output stage further includes a clamping stage coupled with the input stage and the output circuit, and a feedforward path coupled between the input stage and the output circuit. The clamping stage is configured to maintain the output level of the output stage to be approximately equal to the input stage output, while the feedforward path is configured to stabilize the output stage output at high frequencies.
In one embodiment, the first current compensation circuit further includes a PNP sink transistor coupled with the first current driving stage to sink a first driving stage total collector current from the first current driving stage. The PNP sink transistor is configured to define a first compensation current to compensate for the first bias current wherein the first bias current is about equal to a total collector current of the first current driving stage divided by a PNP beta factor. Further, the second current compensation circuit includes an NPN source transistor coupled with the second current driving stage to supply a second driving stage total collector current from the second current driving stage. The NPN source transistor is configured to define a second compensation current to compensate for the second bias current wherein the second bias current is about equal to a total collector current of the second current

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