Output queued switch with a parallel shared memory, and...

Multiplex communications – Communication over free space – Having a plurality of contiguous regions served by...

Reexamination Certificate

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C370S390000, C370S429000

Reexamination Certificate

active

07835334

ABSTRACT:
A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node.

REFERENCES:
patent: 5285444 (1994-02-01), Sakurai et al.
patent: 5337308 (1994-08-01), Fan
patent: 5383181 (1995-01-01), Aramaki
patent: 5714866 (1998-02-01), S et al.
patent: 5724352 (1998-03-01), Cloonan et al.
patent: 5732087 (1998-03-01), Lauer et al.
patent: 5896380 (1999-04-01), Brown et al.
patent: 6061673 (2000-05-01), Tang
patent: 6067654 (2000-05-01), Nakano et al.
patent: 6094430 (2000-07-01), Hoogenboom
patent: 6122279 (2000-09-01), Milway et al.
patent: 6188686 (2001-02-01), Smith
patent: 6263053 (2001-07-01), Kuftedjian et al.
patent: 6324165 (2001-11-01), Fan et al.
patent: 6331981 (2001-12-01), Harth et al.
patent: 6349098 (2002-02-01), Parruck et al.
patent: 6370162 (2002-04-01), Takahashi et al.
patent: 6473428 (2002-10-01), Nichols et al.
patent: 6570854 (2003-05-01), Yang et al.
patent: 6580721 (2003-06-01), Beshai
patent: 6661773 (2003-12-01), Pelissier et al.
patent: 6751219 (2004-06-01), Lipp et al.
patent: 6885657 (2005-04-01), Rabenko et al.
patent: 7420969 (2008-09-01), Siu et al.
patent: 2002/0064130 (2002-05-01), Siu et al.
patent: 2002/0064172 (2002-05-01), Siu et al.
patent: 2004/0246891 (2004-12-01), Kay et al.
Sundar Iyer, et al.; “Analysis of a Packet Switch with Memories Running Slower than the Line-Rate”; Computer Systems Laboratory, Stanford University, Stanford, CA 94305-9030;9 pages.
Sundar Iyer; “Analysis of a Package Switch with Memories Running Slower than the Line Rate” Copyright 2000 by Sundar Iyer; pp. 1-47.

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