Output preconditioning circuit with an output level latch and a

Details Output preconditioning circuit with an output level latch and a Output preconditioning circuit with an output level latch and a

1994-07-29

1996-09-24

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Accelerating switching

326 17, 326 56, H03K 1704

Patent

active

055594654

ABSTRACT:
An output preconditioning circuit with an output level latch is provided to precondition the output to an intermediate level and to clamp the output to that level before the actual data from a memory cell arrives at the output. Since the actual data has to charge or discharge the output from some intermediate level rather than the maximum output swing level or the minimum output swing level, as in the normal case, this results in a reduced delay in charging or discharging the output. The output preconditioning circuit which may be coupled to a heavy load or a light load can eliminate oscillation of the output because of the output level latch. The preconditioning system includes (1) a level sense circuit for sensing a voltage level of the circuit output and comparing the voltage level to two different reference voltages and (2) a preconditioning circuit including a latch circuit for latching the values in response to the comparison and a driver-and-clamp circuit for clamping the circuit output to an intermediate voltage level when the values indicate that the circuit output is out of the desired range.

REFERENCES:
patent: 4983860 (1991-01-01), Yim et al.
patent: 4988888 (1991-01-01), Hirose et al.
patent: 4992677 (1991-02-01), Ishibashi et al.
patent: 5057711 (1991-10-01), Lee et al.
patent: 5124577 (1992-06-01), Davis et al.
patent: 5151621 (1992-09-01), Goto
patent: 5237213 (1993-08-01), Tanoi
patent: 5311076 (1994-05-01), Park et al.
patent: 5336947 (1994-08-01), Lehning
patent: 5418472 (1995-05-01), Moench
F. Miyaji, K. Seno, H. Satoh, Y. Tomo, M. Sasaki and K. Kobayashi, "A 14ns 0.35 um 4Mb CMOS SRAM with an Output Preconditioning Circuit," ULSI R&D Group, Atsugi Technology Center, Sony Corp.
L. Childs, K. Jones, R. Chang, M. Bader, R. Yu and K. Wang, "A 16ns 512Kx8 CMOS SRAM with Power Saving and Output Buffer Noise Reduction Features," Memory Product Division, Motorola Inc.

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