Output pre-driver for reducing totem pole current

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S112000, C327S403000, C327S408000, C326S082000, C326S087000

Reexamination Certificate

active

06236245

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to output buffers, and more specifically, to an output driver for reducing totem pole current.
BACKGROUND
A totem pole output is one that is connected through active devices to both sides of the circuit's power supply. Only one of the active devices can be biased on at any given time. When one is on, it effectively connects the output directly to the positive side of the power supply; when the other is on the output is connected directly to the negative side of the supply.
The advantage of totem pole outputs is that they have very low output impedance at both high and low output levels. This results in good noise immunity and the capability for high-speed operation.
A typical output circuit has a NPN transistor with its emitter connected to ground and its collector connected to the positive side of the power supply through a load resistor. When the transistor is biased on, the output is a low impedance to ground just as in the case of the totem pole output. However, when the transistor is biased off, the load resistor is a significant impedance across which noise voltages can be developed. Also, when driving a capacitive load, the load resistor, along with the load, has a time constant which increases the time for the output voltage to build up to its maximum level.
FIG. 1
is a prior art buffer having a totem pole output. The buffer includes an N-type metal oxide semiconductor (NMOS) and a P-type MOS (PMOS)
120
coupled in series between V
cc
130
, the voltage supply, and ground
140
. The output is coupled between the NMOS
110
and PMOS
120
. The gate of the PMOS
120
receives the pull-up signal
150
, while the gate of the NMOS
110
receives the pull-down signal
160
. Thus, when the buffer is switched from a pull-up to a pull-down, the PMOS
120
is turned off while the NMOS
110
is turned on. Because it takes some time for the PMOS
120
or NMOS
110
to fully turn off, there is a period when both devices are partially on, and this causes a totem pole current.
FIG. 2
illustrates the pull-up signal
210
and pull-down signal
220
for the circuit of FIG.
1
. As can be seen from
FIG. 2
, there is a period when both the NMOS and PMOS are partially on, t
overlap
230
, i.e. the gate input to the NMOS is above the threshold voltage, while the gate input to the PMOS is below the threshold voltage. This overlapping period
230
produces a totem pole current. This may result in ground bounce. Ground bounce occurs when the chip ground moves up and down with respect to the PC-board and system ground. This changes the output Low voltage and changes the apparent input voltage, effectively adding to or subtracting from the input threshold voltage. This is disadvantageous because it may cause a false reading, and it increases power consumption. Therefore, it would be advantageous to have an output buffer that did not produce a totem pole current.
SUMMARY OF THE INVENTION
An output driver to reduce totem pole current is described. The output driver comprises a first delay element outputting a delayed first driver signal, and a first selection unit receiving as an input the first driver signal and the delayed first driver signal. The output driver further comprises a second delay element outputting a delayed second driver signal and a second selection unit receiving as an input the second driver signal and the delayed second driver signal. A selection signal for the first selector is the first driver signal, and the selection signal for the second selector is an inverted first driver signal, such that a path that is not presently driving is switched off first, prior to the opposing driver being turned on.


REFERENCES:
patent: 4825101 (1989-04-01), Walters, Jr.
patent: 4910416 (1990-03-01), Salcone
patent: 4961010 (1990-10-01), Davis
patent: 5450019 (1995-09-01), McClure et al.
patent: 5471150 (1995-11-01), Jung et al.
patent: 5486782 (1996-01-01), Chan
patent: 5949269 (1999-09-01), Allen

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