Output pad precharge circuit for semiconductor devices

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C365S203000

Reexamination Certificate

active

06281719

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit devices, particularly integrated circuit memory devices, having output terminals, and to circuitry for precharging the output terminals to reduce the time needed to drive output signals on such output terminals.
2. Description of Related Art
Integrated circuits have output terminals, typically referred to as output pads, on which signals are driven for access by external circuitry. The output pads typically have significant capacitance. For this reason output driver circuitry is included that uses large transistors to drive the output pads, or that consumes a significant amount of time in driving in the output pads to the desired signal level. As integrated circuits become more complex, and operate at higher speeds, the area and speed trade-off involved in the output drivers becomes more critical.
For integrated circuit memory devices, the read access time is becoming a critical parameter. The read access time is measured from the beginning of a read cycle until the time that data is available on the output pads for use by the external circuitry.
The access time can be considered to have two components. The first component consists of the amount of time between the time a read signal is received by the device, and the time internal data is available to the output driver. The second component consists of the amount time that takes the output driver to change the level of the output pad to a level acceptable for use by external circuits. The first component is largely controlled by the architecture of the memory device. The second component involves the performance of the output driver, and the charge on the pad when the output driver is enabled. Thus, if the output voltage is to be driven to a high level, and the pad is charged near ground at the beginning of the cycle, then the time required to reach a suitable voltage level is longer. Likewise, if the output voltage is to be driven to a low level, and the pad is charged near a high level at the beginning of the cycle, then the time required is longer.
It is desirable to ensure that the output pad is precharged to a level near the middle of the voltage range. In this way, the output driver has a shorter distance to move the voltage on the pad in the worst-case, and can accomplish its task in a shorter, more predictable time interval. In this application, unless apparent from the context, the word “precharge” is intended to the both charging up from a low voltage to a higher voltage, and charging down from a high voltage to a lower voltage. In this way, we avoid repeatedly using such phrases as “precharge and/or predischarge.”
Background concerning technology that has been developed to address the problem of output driver precharge can be found in U.S. Pat. No. 5,151,621 entitled HIGH-SPEED OUTPUT BUFFER UNIT THAT PRELIMINARILY SETS THE OUTPUT VOLTAGE LEVEL; U.S. Pat. No. 5,058,066 entitled OUTPUT BUFFER PRECHARGE CIRCUIT FOR DRAM; U.S. Pat. No. 4,988,888 entitled CMOS OUTPUT CIRCUIT WITH INTERMEDIATE POTENTIAL SETTING MEANS; U.S. Pat. No. 5,204,838 entitled HIGH SPEED READOUT CIRCUIT; U.S. Pat. No. 5,377,149 entitled OUTPUT PRECHARGE CIRCUIT FOR MEMORY.
Taking the '621 patent for example, the precharge circuitry suffers the disadvantage that it relies on the same driver for precharging as used for driving the actual data. This has the disadvantage that as speeds increase, undesirable noise can be injected into the read path. The '621 patent inserts transmission gates between the internal circuitry and output buffer to prevent this problem with noise. However, the transmission gates consume significant area in the output driver, offsetting some of the benefits of the precharge circuitry. The '621 patent also suffers the disadvantage that it relies on sensing the previous output data value, and storing such value in a latch (e.g.
31
d
). It is possible that the voltage on the output terminal could drift between the read cycles, causing the precharge circuit to be initialized incorrectly.
Accordingly, it is desirable to provide a more efficient pull up and pull down circuit for use in precharging output terminals of integrated circuits, which operates quickly and with predictable timing consumes less standby current, and uses minimum space on integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides an output driver for an integrated circuit which performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. Furthermore, the invention provides a low-power and compact designed not taught in the prior art.
The invention can be characterized as a driver for an output of integrated circuit. It includes a driver to supply an output signal to the output. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit is coupled the output, and responsive to the sense circuit, to drive the output to near the threshold in response to the initial state and before the output signal is supplied the output.
In various embodiments, the precharge circuit includes a pull up circuit and a down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold. Logic is responsive to the control signal from the detector to turn off the precharge circuit.
The circuit further includes logic that produces a control signal in response to a data output event, such as a read cycle on an integrated circuit memory. The control signal indicates the beginning of the data output event, before data is available from internal circuits responding to the event. The sense circuit is responsive to the control signal indicating the beginning of the event to store the initial state. The logic further produces a second control signal which is used to start and stop the precharge interval. At the beginning of the assertion of the second control signal, the precharge circuit is enabled, and responsive to the stored initial state to turn on either the pull up or the pull down circuit. When the level on the output is near the threshold, the detector turns off the precharge circuit. At the end of the assertion of the second control signal, the precharge circuit is disabled, and the output driver is enabled to supply the output signal to the output.
In one embodiment, the sense circuit comprises a latch that is responsive to a first control signal indicating the beginning of the data output event to store a value indicating the initial state of the output pad. Also, the detector comprises a gate, such as a NOR gate, that is only enabled during assertion of the second control signal.
According to another aspect of the invention, an integrated circuit memory device is provided including a memory array, read circuitry, and an output driver. The sense circuit and precharge circuit described above are included on the integrated circuit memory device to provide for high-speed reading of data.
Accordingly, the present invention provides precharge circuit which operates by detecting an initial value of the output pad at the beginning of the data output event, and pulling up or pulling down the voltage on the output pad, in response to the initial value during a timed precharge interval, prior to the enabling of the output driver for the data output event. The invention provides a precharge circuit having predictable timing, supporting high-speed opera

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