Output multiplexing implementation for a simultaneous operation

Details Output multiplexing implementation for a simultaneous operation Output multiplexing implementation for a simultaneous operation

1999-10-19

2000-09-12

Nguyen, Viet Q.

Static information storage and retrieval

Floating gate

Particular connection

36518523, 36518533, 36523003, 36523004, 36523006, 36523008, G11C 1604

Patent

active

061186988

ABSTRACT:
A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.

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