Output multiplexer having one gate delay

Details Output multiplexer having one gate delay Output multiplexer having one gate delay

1982-12-09

1984-12-04

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

307243, H04J 1500

Patent

active

044868804

ABSTRACT:
A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.

REFERENCES:
patent: 3838296 (1974-09-01), McLeod

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