Output matched LDMOS power transistor device

Details Output matched LDMOS power transistor device Output matched LDMOS power transistor device

1998-12-02

2001-01-23

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

C257S341000, C257S401000

Reexamination Certificate

active

06177834

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains generally to the field of radio frequency power transistors, and more specifically to methods and apparatus for output impedance matching of an LDMOS power transistor device.
2. Background
The use of radio frequency (RF) amplifiers, for example, in wireless communication networks, is well known. With the considerable recent growth in the demand for wireless services, such as personal communication services (PCS), the operating frequency of wireless networks has increased dramatically and is now well into the gigahertz (GHz) frequencies. At such high frequencies, LDMOS transistors have been preferred for RF power amplification devices, e.g., in antenna base stations.
In a typical deployment, an LDMOS RF power transistor device generally comprises a plurality of electrodes formed on a silicon die, each electrode comprising a plurality of interdigitated transistors. The individual transistors of each electrode are connected to respective common input (gate) and output (drain) terminals for each electrode. The die is attached, by a known eutectic die attach process, atop a metallic (source) substrate, which is itself mounted to a metal flange serving as both a heat sink and a ground reference. Respective input (gate) and output (drain) lead frames are attached to the sides of the flange, electrically isolated from the metal (source) substrate, wherein the input and output lead frames are coupled to the respective electrode input and output terminals on the silicon die by multiple wires (i.e., bonded to the respective terminals and lead frames).
Impedance matching the input and output electrode terminals to the respective input and output lead frames is crucial to proper operation of the amplifier device, especially at high operating frequencies.
By way of illustration,
FIG. 1
shows a simplified electrical schematic of an unmatched LDMOS device, having an input (gate) lead
12
, an output (drain) lead
14
and a source
16
through an underlying substrate. Transmission inductance through the input path, e.g., a plurality of bond wires connecting the input lead
12
to the common input terminal of the respective transistor fingers, is represented by inductance
18
. Output inductance through the output path, e.g., a plurality of bond wires connecting the common output terminal of the respective transistors to the output lead
14
, is represented by inductance
20
.
FIG. 2
shows a known (matched) LDMOS power transistor device
40
. The device
40
includes an input (gate) lead
42
, output (drain) lead
44
and metallic (source) substrate
47
attached to a mounting flange
45
. A first plurality of wires
48
couple the input lead
42
to a first terminal of an input matching capacitor
46
. A second terminal of the input matching capacitor
46
is coupled to ground (i.e., flange
45
). A second plurality of wires
52
couple the first terminal of matching capacitor
46
to the respective input terminals
49
of a plurality of interdigitated electrodes
51
formed on a semiconductor die
50
attached to the metallic substrate
47
. By proper selection of the matching capacitor
46
and the series inductance of wires
48
and
52
, the input impedance between the input lead
42
and electrode input terminals
49
can be effectively matched.
Respective output terminals
53
of the electrodes are coupled to the output lead
44
by a third plurality of wires
54
. In order to impedance match the output of the device, a shunt inductance is used. Towards this end, the output lead
44
is coupled to a first terminal of a DC blocking capacitor
58
(i.e., an AC short) by a fourth plurality of wires
60
, the blocking capacitor
58
having a substantially higher value than the input matching capacitor
46
.
FIG. 3
shows a schematic circuit representation of the device of
FIG. 2
, wherein the transmission inductance through the respective pluralities of wires is designated by the corresponding reference numbers of the wires in FIG.
2
.
For “lower frequency” applications, e.g., 1500 MHz, the LDMOS device
40
of
FIG. 2
may be adequately controlled, but at higher frequencies, e.g., 2 GHz, effective control of the device becomes difficult due to the relatively large series inductance generated through wires
54
to the shunt inductance
60
. Further, because there is limited physical space on the electrode output terminals
53
, the number of wires
54
connecting the plurality of electrodes
51
to the output lead
44
is thereby limited.
Thus, it would be desirable to provide an LDMOS RF power transistor device in which output matching at relatively high frequencies (e.g., GHz) can be more easily accomplished.
SUMMARY OF THE INVENTION
In accordance with a first aspect of the present invention, an RF power transistor device comprises a semiconductor die having a plurality of electrodes formed thereon, the electrodes having respective output terminals. A conductive island is provided adjacent the semiconductor die and is coupled to the electrode output terminals by a first plurality of conductors. A shunt inductance match is coupled from the conductive island by a second plurality of conductors to a blocking capacitor and an output lead is independently coupled to the conductive island by a third plurality of conductors.
By way of example, in a preferred embodiment, an LDMOS RF power transistor device includes a semiconductor die having a plurality of interdigitated electrodes formed thereon, the electrodes each having respective input terminals and output terminals. An input lead is coupled to a first terminal of an input matching capacitor by a first plurality of conductors (e.g., bond wires), with a second terminal of the matching capacitor coupled to a ground. The first terminal of the matching capacitor is also coupled to the electrode input terminals by a second plurality of conductors. A conductive island isolated from the ground is coupled to the electrode output terminals by a third plurality of conductors. Output matching of the device is provided by a shunt inductance formed by a fourth plurality of conductors coupling the conductive island to an output blocking capacitor, the blocking capacitor having a second terminal coupled to ground. An output lead is coupled to the conductive island by a fifth plurality of conductors.
The conductive island is preferably disposed adjacent the semiconductor die, and the output blocking capacitor is disposed between the conductive island and output lead, such that transmission inductance through the respective third and fourth pluralities of conductors coupling the electrode output terminals to the blocking capacitor is sufficiently small to allow for output impedance matching of the transistor device at relatively high operating frequencies.
As will be apparent to those skilled in the art, other and further aspects and advantages of the present invention will appear hereinafter.


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patent: 5309014 (1994-05-01), Wilson
patent: 5917705 (1999-06-01), Kirschbauer
patent: 6025277 (2000-02-01), Chen et al.
patent: 0 015 709 A1 (1980-09-01), None
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Patent Abstracts of Japan, vol. 011, No. 182 (E-515), Jun. 11, 1987 (1987-06-11) & JP 62 013041 A (Mitsubishi Electric Corp.), Jan. 21, 1987 (1987-01-21) abstract.
Patent Abstracts of Japan, vol. 015, No. 355 (E-1109), Sep. 9, 1991 (1991-09-09) & JP 03 138953 A (NEC Corp.), Jun. 13, 1991 (1991-06-13) abstract.

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