Output macrocell for programmable logic device

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307468, H03K 19177

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active

048945633

ABSTRACT:
A programmable logic device having an AND array receiving inputs and having programmable product term lines output to an OR array, and an output macrocell associated with each of a plurality of input/output pins. Each macrocell has a plurality of sum term lines from the OR array which may selectively be combined or left distinct, and a plurality of flip-flop registers receiving input from the combined or distinct sum lines. Each flip-flop has product term programmable clock, reset and preset lines and a dedicated feedback line into the AND array. A selection circuit is provided for selecting combinatorial output from one or more sum term lines or registered output from one of the flip-flop registers. A product term programmable output enable selects either the output or disables the output buffer so that a pin may receive input signals fed through a dedicated line into the AND array.

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Logic Diagrams for Monolithic Memories 32VX10, 20RA10 and 20RS10 Logic Devices.

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