Output line arrangement structure of row decoding array

Details Output line arrangement structure of row decoding array Output line arrangement structure of row decoding array

1999-12-30

2001-01-30

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S063000

Reexamination Certificate

active

06181636

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to arrangement of bus lines transmitting a signal used to determine a word line address of a plurality of memory cell arrays of a semiconductor memory device, and in particular to an output line (bus) arrangement structure of a row decoding array.
2. Description of the Background Art
An output signal of a row decoding array is a word line enable signal Pxi and a word line disable signal /Pxi. In general, a high voltage and an inside voltage are employed as an operational voltage, respectively at enable and disable states. A functional block of receiving the two signals, and connecting them to a final word line is a sub-word line driver (SWD).
As illustrated in
FIG. 1
, a conventional output line (bus) arrangement structure of the row decoding array is controlled according to the word line enable signal Pxi and the word line disable signal /Pxi applied from a word line driver
17
to an output line
15
of the row decoding array in order to drive a cell block
11
including: a unit memory array
12
consisting of a plurality of sub-memory cell arrays
10
and a plurality of sub-word line drivers
13
; and a main row decoder
14
connected to one end portion of the unit memory array
12
, and selects a final word line CWL<
0
> by the sub-word line driver
13
.
Here, each unit memory array
12
employs one output line
15
of the row decoding array. At the same time, a unit bit sense amp
16
consisting of a plurality of bit sense amps is positioned below the output line
15
of the row decoding array. In addition, when a row address of 2 bits is used for decoding the word line driver
17
, as shown in
FIG. 1
, four unit memory arrays
12
, four word line drivers
17
and four output lines of the row decoding array are used.
However, in the conventional output line arrangement structure for the row decoding array, one word line driver
17
must control the four unit memory arrays
12
, and thus a delay corresponding to four times of a unit memory array word line transmission speed is generated. As a result, a high speed operation is difficult to perform. In addition, the output line
15
of the row decoder array is arranged at every unit bit sense amp
16
, and thus an area for line arrangement is increased by four times.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an output line arrangement structure of a row decoding array which can decrease an area when arranging a memory array, and implement a high speed operation according to load reduction of a word line control signal, by arranging a part of output lines at one side end portion of a cell array, and another part of the output lines at a middle portion of the cell array (bit line divider), in a bus structure of word line enable and disable signals used for the row decoding array.
In order to achieve the above-described object of the present invention, there is provided an output line arrangement structure of a row decoding array wherein a part of output lines of the row decoding array controls a unit memory array sub-word line driver at upper and lower ends through a bit line divider, another part thereof controls a unit memory array sub-word line driver through one side end unit bit sense amp, thereby selecting a final word line, in a unit memory array consisting of a plurality of memory cells.
Here, the output line of the row decoding array controls at least two unit memory arrays.


REFERENCES:
patent: 4797858 (1989-01-01), Wang et al.
patent: 5089992 (1992-02-01), Shinohara
patent: 5253203 (1993-10-01), Partovi et al.
patent: 5280443 (1994-01-01), Hidaka et al.
patent: 5367488 (1994-11-01), An
patent: 5461589 (1995-10-01), Hidaka et al.
patent: 5473566 (1995-12-01), Rao
patent: 5561623 (1996-10-01), Ema
patent: 5652723 (1997-07-01), Dosaka et al.
patent: 5689473 (1997-11-01), Toda
patent: 5703821 (1997-12-01), Baroni et al.
patent: 5717645 (1998-02-01), Kengeri et al.
patent: 5798978 (1998-08-01), Yoo et al.
patent: 5825704 (1998-10-01), Shau
patent: 5889724 (1999-03-01), Khang et al.

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