Output level adjustment means for low fanout ECL lacking emitter

Details Output level adjustment means for low fanout ECL lacking emitter Output level adjustment means for low fanout ECL lacking emitter

1981-05-01

1984-03-06

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, H03K 19086, H03K 19092

Patent

active

044356544

ABSTRACT:
A complex logic circuit which fulfills the requirements of high-speed operation, low power consumption and simplicity in circuit setup, includes a first ECL (emitter coupled logic) circuit and a second ECL circuit. The first ECL circuit which drives relatively light loads does not have an emitter follower output circuit in the output thereof. The second ECL circuit which drives relatively heavy loads has an emitter follower output circuit in the output thereof. A level shift means is connected between the load resistor of the first ECL circuit and a point of operation potential, and the voltage drop across the level shift means is set to be substantially equal to the voltage across the base and emitter of the emitter follower output transistor of the second ECL circuit. Thus, the signal levels of the first and second ECL circuits can be made to coincide.

REFERENCES:
patent: 3529294 (1970-09-01), Zuk
patent: 3573488 (1971-04-01), Beelitz
patent: 3648064 (1972-03-01), Mukai et al.
patent: 3942033 (1976-03-01), Swiatowiec et al.
patent: 4255672 (1981-03-01), Ohno et al.
Camenzind, "Circuit Design for Integrated Electronics", Addison-Wesley Pub. Co., pp. 157-159, 1968.

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