Output interface for a three-state logic circuit in an integrate

Details Output interface for a three-state logic circuit in an integrate Output interface for a three-state logic circuit in an integrate

1983-12-12

1985-11-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307473, 307578, H03K 424, H03K 1706, H03K 19096, H03K 458

Patent

active

045556440

ABSTRACT:
An output interface which includes a capacitor which is charged to a relatively high voltage by a voltage source which may have a high internal impedance, and a switching circuit which is controlled by an output of the associated logic circuit and which connects the capacitor with a gate electrode of a transistor of the final stage of the interface in order to bias it at a higher voltage than that of the power supply only during a prespecified logic state of the logic circuit and which keeps the capacitor essentially isolated (i.e.--floating) during any other logic state.

REFERENCES:
patent: 3889135 (1975-06-01), Nomiga et al.
patent: 4291242 (1981-09-01), Schriber
patent: 4430586 (1984-02-01), Hebenstreit
patent: 4468576 (1984-08-01), Takemae
patent: 4477741 (1984-10-01), Moser, Jr.

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