Output interface circuit

Details Output interface circuit Output interface circuit

2001-08-27

2002-09-24

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S333000, C327S099000, C327S538000, C326S063000, C326S080000

Reexamination Certificate

active

06456147

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output interface circuit and more particularly, to an output interface circuit to be placed between an internal circuit or circuits and an external terminal, which is used as an interface circuit for/in outputting an output signal of the internal circuit or circuits to the external output terminal.
2. Description of the Related Art
In recent years, the need to increase the integration scale of electronic elements/components on a semiconductor integrated circuit device (which is referred as a “LSI” hereinafter) and to reduce the power consumption thereof has become stronger. To meet the need, various techniques have been developed to lower the supply voltage for a LSI from popular 5 V to a lower one such as 3.3 V or 2 V.
A LSI is usually built into an external device or apparatus and therefore, a LSI is supplied with its supply voltage from the external device/apparatus. In this case, the LSI is supplied with a conventional supply voltage of 5 V or a recent one of 3.3 V or 2 V. This means that the value of the supply voltage for a LSI varies dependent on what value of voltage an external device/apparatus supplies to a LSI incorporated. Taking this fact into consideration, a proper contrivance needs to be provided in such a way that a LSI operates normally not only at a higher supply voltage of 5 V but also at a lower one of 3.3 V or 2 V.
Recently, when the designed supply voltage of a LSI is 3.3 or 2 V, a voltage-lowering circuit has been often provided in the power supply circuit of a LSI to lower the incoming supply voltage of 5 V to 3.3 or 2 V. In this case, a desired supply voltage of 3.3 or 2 V is produced by the voltage-lowering circuit built in the LSI and then, it is supplied to the internal circuit(s) thereof.
In this specification, a supply voltage (e.g., 3.3 or 2 V) generated and supplied inside a LSI itself is termed an “internal supply voltage” while a supply voltage (e.g., 5 V) supplied from an external device/apparatus located outside the LSI is termed an “external supply voltage”. Moreover, a circuit for generating an “internal supply voltage” inside a LSI is termed an “internal power supply circuit” while a circuit for generating an “external supply voltage” in an external device/apparatus located outside the LSI is termed an “external power supply circuit”.
Some prior-art output interface circuits of this type are capable of normal operation at both an internal supply voltage of 3.3 V or 2 V and an external supply voltage of 5 V. These circuits are termed “voltage tolerant circuits”, an example of which is shown in FIG.
1
.
In
FIG. 1
, a prior-art LSI
200
is incorporated into a specific external device or apparatus (not shown). Only an external power supply circuit
69
of the external device is shown in
FIG. 1
for simplification of illustration.
Practically, the prior-art LSI
200
comprises various internal circuits to realize its specific functions. However, only one of the internal circuits is shown in
FIG. 1
with the reference numeral
61
for simplification. Although the LSI
200
comprises practically various external terminals for outputting its output signals, only one of them is shown in
FIG. 1
with the reference numeral
67
. The terminal
67
is used to derive an output signal S
61
of the internal circuit
61
(i.e., the LSI
200
). The LSI
200
further comprises a prior-art output interface circuit
62
and an internal power supply circuit
68
.
The output interface circuit
62
provides a specific interface function between the internal circuit
61
and the external output terminal
67
. The internal power supply circuit
68
supplies a specific internal supply voltage V
INT
(=3.3 V) to the inside of the LSI
200
including the internal circuit
61
and the output interface circuit
62
.
The external power supply circuit
69
, which is incorporated into the external device, is located outside the LSI
200
. The circuit
69
supplies a specific external supply voltage V
INT
(=5 V or 3.3 V) to the inside of the LSI
200
including the output interface
The output interface circuit
62
comprises a 5V-system output buffer circuit
63
that provides its optimum operation at a supply voltage of 5 V and a 3.3V-system output buffer circuit
64
that provides its optimum operation at a supply voltage of 3.3 V. These two buffer circuits
63
and
64
are alternately activated or used dependent on the current value (5 V or 3.3 V) of the external supply voltage V
EXT
supplied by the external power supply circuit
69
.
The internal circuit
61
is supplied with the internal supply voltage V
INT
(3.3 V) from the internal power supply circuit
68
. The 5V-system output buffer circuit
63
is supplied with the external supply voltage V
EXT
(5 V or 3.3 V) from the external power supply circuit
69
and the internal supply voltage V
INT
(3.3 V) from the internal power supply circuit
68
. The 3.3V-system output buffer circuit
64
is supplied with the external supply voltage V
EXT
(5 V or 3.3 V) or the internal supply voltage V
INT
(3.3 V) by way of a switch
65
.
The output signal S
61
of the internal circuit
61
is applied to both the 5-system output buffer circuit
63
and the 3.3V-system output buffer circuit
64
. In response to the signal S
61
, the 5V-and 3.3V-system output buffer circuits
63
and
64
output their output signals S
63
and S
64
, respectively. One of the signals S
63
and S
64
is sent to the external output terminal
67
by way of a switch
66
.
Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETS) that constitute the 5V-system output buffer circuit
63
are different in characteristics from those that constitute the 3.3V-system output buffer circuit
64
. Specifically, the maximum supply voltage applied to the circuit
63
is greater than that applied to the circuit
64
. Thus, the gate insulator thickness of the MOSFETs of the circuit
63
is larger than that of the circuit
64
and at the same time, the logic threshold of the MOSFETs of the circuit
63
is higher than that of the circuit
64
.
Due to the characteristic difference, when the external supply voltage V
EXT
is 5 V, the switch
66
is controlled to interconnect the 5V-system output buffer circuit
63
to the external output terminal
67
and at the same time, the switch
65
is controlled to interconnect the 3.3V-system output buffer circuit
64
to the internal power supply circuit
68
. As a result, the output signal S
63
of the circuit
63
operable at the external supply voltage V
EXT
of 5 V is derived from the output terminal
67
. The output signal S
64
of the circuit
64
operable at the internal supply voltage V
INT
of 3.3 V is not sent to the output terminal
67
.
When the external supply voltage V
EXT
is 3.3 V, the switch
66
is controlled to interconnect the 3.3V-system output buffer circuit
64
to the external output terminal
67
and at the same time, the switch
65
is controlled to interconnect the 3.3V-system output buffer circuit
64
to the external power supply circuit
69
. As a result, the output signal S
64
of the circuit
64
operable at the external supply voltage V
EXT
of 3.3 V is derived from the output terminal
67
. The output signal S
63
of the circuit
63
is not sent to the output terminal
67
. This is because the external supply voltage V
EXT
of 3.3 V is supplied to the circuit
63
and thus, the signal S
63
has undesired characteristics.
As explained above, with the prior-art LSI
200
of
FIG. 1
, when the external supply voltage V
EXT
is 5 V, the output signal S
63
of the 5V-system buffer circuit
63
operable optimally at 5 V is derived from the output terminal
67
. When the external supply voltage V
EXT
is 3.3 V, the out put signal S
64
of the 3.3V-systembuffer circuit
64
operable optimally at 3.3 V is derived from the output terminal
67
. Thus, an optimum interface operation is provided independent of whether the external supply voltage V
EXT
is 5 V or 3.3 V.
The switches
65
and
6

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