Output ESD protection with high-current-triggered lateral SCR

Details Output ESD protection with high-current-triggered lateral SCR Output ESD protection with high-current-triggered lateral SCR

1997-02-04

1998-05-19

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, H02H 900

Patent

active

057543810

ABSTRACT:
An output buffer in a CMOS circuit includes an output pad; a VDD line which supplies a first supply voltage; a VSS line which supplies a second supply voltage; a first MOS device connected between the VDD line and the output pad; a second MOS device connected between the VSS line and the output pad; a lateral SCR device connected from the output pad to one of the VDD and VSS lines and in parallel with one of the first and second MOS devices; and a bypass diode connected to the other of the VDD and VSS lines and to the lateral SCR device.

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