Output enable signal generating circuit and method

Details Output enable signal generating circuit and method Output enable signal generating circuit and method

2008-12-31

2010-12-07

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100

Reexamination Certificate

active

07848179

ABSTRACT:
An output enable signal generating circuit including a first count value generation unit that provides a first count value by executing a counting operation, starting from an initial count value corresponding to a CAS latency information, the counting operation being executed in response to an internal clock signal, a second count value generation unit that provides a second count value that is counted in response to an external clock signal and an output enable signal generation unit for generating an output enable signal that is activated at every timing when the second count value and the first count value become equal to each other, in response to each of a plurality of read commands.

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Notice of Preliminary Rejection issued from Korean Intellectual Property Office on Aug. 28, 2009 with an English Translation.
Notice of Allowance issued from Korean Intellectual Property Office on Oct. 31, 2009.

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