Output driver with over voltage protection

Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific voltage responsive fault sensor

Reexamination Certificate

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Details

C361S086000

Reexamination Certificate

active

06724595

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to output drivers and, more particularly, to an output driver with over voltage protection.
2. Description of the Related Art
An output driver is a circuit that sources a substantial current to, or sinks a substantial current from, a capacitive external circuit to drive an output signal onto the external circuit. In addition, output drivers are commonly utilized to provide an interface between a low-voltage digital circuit, such as a circuit that outputs a logic high as a 1.5V signal, and a high-voltage external circuit, such as a circuit that inputs a logic high as a 3.3V signal.
FIG. 1
shows a schematic diagram that illustrates a simple prior-art output driver
100
. As shown in
FIG. 1
, driver
100
includes a PMOS transistor
110
and a NMOS transistor
112
. PMOS transistor
110
has a gate, a source connected to an I/O power-supply voltage VDDIO, such as 3.3V, and a drain connected to an external node EXT.
The source and drain of PMOS transistor
110
are formed in an n-type material, such as a well or substrate, which is connected to the I/O power-supply voltage VDDIO. In addition, a channel region is defined between the source arid drain in the n-type material, and a layer of gate oxide is formed over the channel region to isolate the gate from the channel region.
NMOS transistor
112
has a gate, a source connected to ground, and a drain connected to the external node EXT. The source and drain of NMOS transistor
112
are formed in a p-type material, such as a well or substrate, which is connected to ground. In addition, a channel region is defined between the source and drain in the p-type material, and a layer of gate oxide is formed over the channel region to isolate the gate from the channel region.
In operation, when a logic low is output from a digital circuit, the voltage on the gate of PMOS transistor
110
turns off PMOS transistor
110
, while the voltage on the gate of NMOS transistor
112
turns on NMOS transistor
112
. When NMOS transistor
112
turns on, transistor
112
sinks current from the external node EXT, thereby pulling the voltage on the external node EXT down to ground.
On the other hand, when a logic high is output from the digital circuit, the voltage on the gate of PMOS transistor
110
turns on PMOS transistor
110
, while the voltage on the gate of NMOS transistor
112
turns off NMOS transistor
112
. When PMOS transistor
110
turns on, transistor
110
sources current to the external node EXT, thereby pulling up the voltage on the external node EXT to the I/O power supply voltage VDDIO, e.g., 3.3V.
One problem with driver
100
is that driver
100
lacks over voltage protection, and thus can not be connected to an external circuit, such as a PCI bus, that carries voltages that are substantially higher than the I/O power supply voltage VDDIO. One reason for this is that if driver
100
were connected to such a circuit, the higher voltages would destroy the oxide layer of transistor
112
.
For example, assume that the external node EXT of driver
100
is connected to a PCI bus that experiences a maximum voltage of 5.5V. Further assume that driver
100
is turned off by placing the I/O power supply voltage VDDIO on the gate of PMOS transistor
110
, and ground on the gate of NMOS transistor
112
. Additionally assume that the I/O power supply voltage VDDIO is equal to 3.3V.
With 3.3V MOS transistors, destructive oxide breakdown typically occurs when the voltage dropped across the layer of gate oxide exceeds approximately 4.2V. In the present example, with ground on the gate of transistor
112
and 5.5V on the drain of transistor
112
, 5.5V are dropped across the layer of gate oxide. Since a value of 5.5V is well above the destructive breakdown level of 4.2V, the higher voltage destroys the gate oxide layer.
Another reason that driver
100
can not be connected to an external circuit that sees higher voltages is that transistor
112
sinks a current at these voltages due to punch through. The higher voltage on the drain of transistor
112
increases the drain depletion region to the point where the source and drain depletion regions overlap. This condition, known as punch through, allows current to flow from the drain to the source region.
With 3.3V MOS transistors, punch through typically occurs when the drain-to-source voltage exceeds, approximately 3.7V. In the present example, with ground on the source of transistor
112
and 5.5V on the drain of transistor
112
, the drain-to-source voltage is equal to 5.5V. Since a value of 5.5V is well above the punch through level of 3.7V, the higher voltage causes a current to flow.
A further reason that driver
100
can not be connected to an external circuit that sees higher voltages is that transistor
110
turns on at these voltages and injects current into the I/O power supply voltage VDDIO. The higher voltage on the drain of transistor
110
causes the drain to temporarily become the source of transistor
110
. As is well known, a PMOS transistor turns on when the gate-to-source voltage is less than the threshold voltage of the transistor, and the source-to-drain voltage is greater than the bias voltage of the transistor.
With 3.3V PMOS transistors, a threshold voltage of −0.7V and a bias voltage of +0.2V are common. In the present example, with 3.3V on the source (temporarily functioning as the drain) and gate of transistor
112
, and 5.5V on the drain (temporarily functioning as the source) of transistor
112
, the gate-to-source voltage is equal to −2.2V (3.3−5.5), while the source-to-drain voltage is equal to +2.2V (5.5−3.3). Since a value of −2.2V is well below the threshold voltage of −0.7V and a value of +2.2V is well above the bias voltage of +0.2V, PMOS transistor
110
turns on.
In addition to turning on, PMOS transistor
110
also has a forward-biased junction to the well/substrate of transistor
110
that produces a large current flow. As is well known, the source-to-well/substrate junction of a PMOS transistor is forward biased when the voltage on the p+ source region is greater than the voltage on the n-type well/substrate by more than the junction voltage of the transistor. With 3.3V MOS transistors, a junction voltage of +0.7V is common.
In the present example, with 3.3V on the well/substrate of transistor
110
and 5.5V on the drain (temporarily functioning as the source) of transistor
110
, the junction voltage is equal to +2.2V (5.5−3.3). Since a value of +2.2V is well above the junction voltage of +0.7V, a large current flows across the junction.
FIG. 2
shows a schematic diagram that illustrates a prior-art output driver
200
that includes over voltage protection circuitry. As a result, output driver
200
can be connected to an external circuit, such as a PCI bus, that carries voltages that are substantially higher than the I/O power supply voltage VDDIO.
As shown in
FIG. 2
, driver
200
includes a PMOS transistor
210
, a NMOS transistor
212
, and a NMOS transistor
214
. PMOS transistor
210
has a gate, a source connected to an I/O power-supply voltage VDDIO, such as 3.3V, and a drain connected to an external node EXT. In addition, the source and drain of transistor
210
are formed in an n-well.
NMOS transistor
212
has a gate connected to the I/O power-supply voltage VDDIO, a source, and a drain connected to the external node EXT. In addition, the source and drain of transistor
212
are formed in a p-type material that is connected to ground. NMOS transistor
214
has a gate, a source connected to ground, and a drain connected to the source of transistor
212
. In addition, the source and drain of transistor
214
are formed in the p-type material that is connected to ground.
Driver
200
also includes a PMOS transistor
220
, a PMOS transistor
222
, and a PMOS transistor
224
. PMOS transistor
220
has a gate, a source connected to the I/O power-supply voltage VDDIO, and a drain conn

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