Output driver control for ROM and RAM devices

Details Output driver control for ROM and RAM devices Output driver control for ROM and RAM devices

1995-11-27

1997-03-04

Zarabian, Amir

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 1300

Patent

active

056086873

ABSTRACT:
The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active. The logic circuit generates an output enable signal, OE, which is coupled to the output drivers of the memory to control float of the output drivers. As a result, a smooth transition from old data to new data is obtained, and system data bus contention in transitions from standby to active modes is eliminated.

REFERENCES:
patent: 5214609 (1993-05-01), Kato
patent: 5307324 (1994-04-01), Nishimoto
patent: 5331593 (1994-07-01), Merritt

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