Output disable control circuit for ECL programmable array logic

Details Output disable control circuit for ECL programmable array logic Output disable control circuit for ECL programmable array logic

1987-04-03

1989-06-20

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307456, 307467, 364716, H03K 19092, H03K 1716, H03K 19088

Patent

active

048411760

ABSTRACT:
The present invention provides circuitry for disabling the output gate of an ECL programmable array logic device so that TTL programming and test signals may be applied to the ECL output node. The disable control circuit is responsive to a control signal to provide pull down current to the ECL output gate. A sensing circuit connected to the ECL output senses the TTL voltage level on the output in the programming mode without disturbing the ECL output in the normal mode.

REFERENCES:
Schmitz/Hingarh, "An ECL Programmable Logic Array", 1984 IEEE International Solid-State Circuits Conference, Feb. 24, 1984, p. 264.
Millhollan/Sung, "A 3.6ns ECL Programmable Array Logic IC", 1985 IEEE International Solid-State Circuits Conference, Feb. 14, 1985, p. 202.

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