Output controller for controlling data output of a...

Details Output controller for controlling data output of a... Output controller for controlling data output of a...

2006-06-29

2008-11-04

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233130, C365S233170, C365S194000, C365S193000, C327S153000, C327S161000

Reexamination Certificate

active

07447108

ABSTRACT:
An output controller includes: an output enable signal generator for generating corresponding ones among a plurality of output enable signals based on a preset column address strobe (CAS) latency, each of the output enable signals having information relating to a delay time from an activation timing of a CAS signal; and an output driving signal generator for receiving the plurality of output enable signals corresponding to the preset CAS latency and outputting rising and falling output driving signals for controlling an output timing of data.

REFERENCES:
patent: 6525988 (2003-02-01), Ryu et al.
patent: 6836437 (2004-12-01), Li et al.
patent: 6930949 (2005-08-01), Schaefer
patent: 7277333 (2007-10-01), Schaefer
patent: 2005/0060487 (2005-03-01), Barth et al.
patent: 2005/0093599 (2005-05-01), Kwak
patent: 2005/0262373 (2005-11-01), Kim
patent: 2007/0019481 (2007-01-01), Park
patent: 2007/0070790 (2007-03-01), Choi
patent: 2004-047066 (2004-12-01), None
patent: 10-2005-0035637 (2005-04-01), None
patent: 10-2005-0041612 (2005-05-01), None
patent: 2005-0105557 (2005-11-01), None
Korean Office Action, with English Translation, issued in corresponding Korean Patent Application No. 2005-0130483, dated on Jul. 25, 2007.

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