Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2008-08-26
2009-12-29
Nguyen, Tuan T (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233110, C365S233120
Reexamination Certificate
active
07639560
ABSTRACT:
An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.
REFERENCES:
patent: 6205086 (2001-03-01), Hanzawa et al.
patent: 6222792 (2001-04-01), Hanzawa et al.
patent: 6556505 (2003-04-01), Tojima et al.
patent: 6862250 (2005-03-01), Shin
patent: 6920080 (2005-07-01), Chung et al.
patent: 7084686 (2006-08-01), Zimlich
patent: 7428185 (2008-09-01), Fujisawa
patent: 2006/0250882 (2006-11-01), Choi et al.
patent: 2003-281888 (2003-10-01), None
Elpida Memory Inc.
McDermott Will & Emery LLP
Nguyen Hien N
Nguyen Tuan T
LandOfFree
Output control signal generating circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Output control signal generating circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output control signal generating circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4127408