Output control signal generating circuit

Details Output control signal generating circuit Output control signal generating circuit

2007-12-25

2007-12-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C327S270000, C327S271000

Reexamination Certificate

active

11523705

ABSTRACT:
An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.

REFERENCES:
patent: 6222792 (2001-04-01), Hanzawa et al.
patent: 6862250 (2005-03-01), Shin
patent: 6920080 (2005-07-01), Chung et al.
patent: 2006/0250882 (2006-11-01), Choi et al.
patent: 2003-281888 (2003-10-01), None

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