Output clock phase-alignment circuit

Details Output clock phase-alignment circuit Output clock phase-alignment circuit

2007-08-07

2007-08-07

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S291000

Reexamination Certificate

active

11187114

ABSTRACT:
A clock generator has a reset circuit and (at least) two dividers, where each divider divides a reference clock signal by a divisor value to generate an output clock signal. The reset circuit generates reset signals for the dividers, where the reset signals are delayed relative to one another by a selected number of reference clock cycles, such that the dividers generate output clock signals having a desired phase offset between them.

REFERENCES:
patent: 5438254 (1995-08-01), Ho et al.
patent: 5822596 (1998-10-01), Casal et al.
patent: 6463013 (2002-10-01), Liu et al.
patent: 6882229 (2005-04-01), Ho et al.
patent: 6894551 (2005-05-01), Johnson
patent: 2004/0027181 (2004-02-01), Watanabe

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