Output circuit with output enabling inputs

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307473, 307475, 307481, H03K 19003

Patent

active

052851176

ABSTRACT:
An output circuit for semiconductor integrated circuit includes control means. It receives an input signal, a reference signal, and a control signal, each having first and second states. When both reference and control signals are in their first state, the control means provides a signal in accordance with the input signal. Output means develops an output signal according to the state of the signal developed by the control means. The timing at which the control signal is placed in its first state is delayed relative to the reference signal in its first state. The time of delay is controlled to change the timing of occurrence of the output signal from the output means.

REFERENCES:
patent: 4587445 (1986-05-01), Kanuma
patent: 4587446 (1986-05-01), Okumura
patent: 4656370 (1987-04-01), Kanuma
patent: 4857765 (1989-08-01), Cahill et al.
patent: 4918339 (1990-04-01), Shigeo et al.
patent: 4983860 (1991-01-01), Yim et al.
U. Tietz and Ch. Schenk: Halbleiter-Schaltungstechnik (Semiconductor Circuitry) Springer-Verlag, Berlin, Heidelberg, N.Y. 1974, p. 505.
1989 International Test Conference, "Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices As Virtual ATE Channels".

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