Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-03-26
2003-12-09
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000, C327S427000
Reexamination Certificate
active
06661260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly to an output circuit of a semiconductor circuit.
2. Description of the Related Art
An output circuit of a semiconductor circuit in which a plurality of semiconductor devices are arranged, is known in Japanese Patent No. 2,646,786 as shown in FIG.
1
. In the output circuit, an N-channel MOS transistor is generally used as an output transistor. The on and off states of the output transistor is controlled by a gate driving circuit. A conventional example of the circuit structure of the gate driving circuit is shown in FIG.
2
.
A conventional semiconductor output circuit shown in
FIG. 1
is comprised of an output transistor
101
, a gate driving circuit
102
which supplies a gate signal to the gate of the output transistor
101
, a control circuit
103
, and a switch
104
connected the source and gate of the output transistor
101
. The control circuit
103
has a protection circuit such as an over-current detecting circuit and an over-temperature detecting circuit and transfers a control signal to the gate driving circuit
102
.
Referring to
FIG. 2
, the gate driving circuit
102
is comprised of first and second inverter circuits and a boosting circuit. The first inverter circuit is comprised of a P-channel transistor
122
and an N-channel transistor
123
connected in series. The second inverter circuit is comprised of a P-channel transistor
105
, an N-channel transistor
121
of a diode connection, and an N-channel transistor
106
. The boosting circuit is comprised of an N-channel transistor
113
, a capacitor C and an N-channel transistor
114
.
The switch
104
is shown in
FIG. 3
, and is comprised of an N-channel transistor
131
, a resistance R
101
and an N-channel transistor
132
.
FIG. 4
shows a modification of the semiconductor output circuit in which the gate driving circuit
102
shown in FIG.
2
and the switch
104
shown in
FIG. 3
are applied to the circuit shown in FIG.
1
. Referring to
FIG. 4
, in the above conventional semiconductor output circuit, when an output transistor on control signal
108
to turn on the output transistor
101
is supplied to the control circuit
103
, a low level is given to the input of the CMOS inverter of the transistors
105
and
106
. In the CMOS inverter, the transistor
105
can be turned on quickly. Through the turning on operation of the CMOS inverter, the output transistor
101
is set to the on state. When the gate driving circuit
102
increases the gate voltage of the output transistor
101
higher than the power supply voltage, the transistor
121
with a diode connection is inversely biased to prevent that the charge flows through the P-channel transistor
105
. Such prevention enables the gate potential of the output transistor
101
to be kept sufficiently high.
When an output transistor off control signal
109
to turn off the output transistor
101
is supplied to the gate driving circuit
102
, the gate voltage of the output transistor
101
becomes the ground potential (0V), and the output transistor
101
is set to the off state. At this time, the N-channel transistor
132
is turned on in response to the output transistor off control signal
109
. As a result, the gate and source of the output transistor
101
are connected to form a short circuit, and it is prevented that the output transistor
101
is turned on when the source potential becomes negative.
In such a conventional semiconductor output circuit, the circuit current flows through the gate driving circuit
102
and the control circuit
103
, even when the output transistor
101
is in the off state. Thus, dark current at the off time becomes large and the power is wastefully consumed. Moreover, as shown in
FIG. 4
, when the output transistor
101
is in the off state and when a negative voltage is applied to an output signal line
110
, there are parasitic current flow routes. One parasitic current flow route is of the power supply line
111
→the transistor
106
→the N-channel transistor
132
→the output signal line
110
, and another parasitic current flow route is of the power supply line
112
→the transistor
113
→transistor
114
→the N-channel transistor
107
→the output signal line
110
. Therefore, the parasitic current in the switching operation of the switch
104
flows wastefully.
It is demanded to prevent the wasteful consumption current which flows through a control circuit and a switching circuit in the off state of the output transistor and the switching operation.
In conjunction with the above description, a gate driving circuit is disclosed in Japanese Examined Patent Application (JP-B-Heisei 6-81025). In the gate driving circuit, the gate of an output transistor of an N-channel MOS transistor is driven which is used as a source output. A voltage boosting circuit carries out a boosting operating of a voltage according to a trigger inputted and gives a boosted voltage to the gate of the output transistor. A first CMOS inverter circuit inputs a low level signal at the same timing as the trigger inputting and an output point is connected with the gate of the said the output transistor. An N-channel MOS transistor for countercurrent prevention is connected to a point between a P-channel MOS transistor of the first CMOS inverter circuit and the output point of the first CMOS inverter circuit, and the gate and drain thereof are connected to those of the P-channel MOS transistor. A second CMOS inverter circuit is provided in parallel to the first CMOS inverter circuit, and an input point is same as that of the first CMOS inverter circuit, and an output point is connected with a background gate of the N-channel MOS transistor for the countercurrent prevention.
Also, a semiconductor integrated circuit is disclosed in Japanese Laid Open Patent application (JP-P2000-58671A). In this reference, a level shift circuit is composed of an N-channel MOSFETs and a P-channel MOSFETs. The N-channel MOSFETs are used for the high side and low side of an output stage circuit. A resistance and a diode are provided in parallel to the N-channel MOSFET on the said high side between the gate and source. The cathode of the diode is connected with the gate and the anode of the diode is connected with the source.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an output circuit of a semiconductor circuit, in which it is possible to prevent wasteful consumption current.
Another object of the present invention is to provide an output circuit of a semiconductor circuit, in which it is possible not to flow a parasitic current when a negative voltage is applied to the source of an output transistor.
In an aspect of the present invention, an output circuit of a semiconductor circuit includes a higher potential side power supply line, a output line on which an output signal is outputted, a control signal line on which a control signal is transferred, a gate signal line on which a gate signal is transferred, an output transistor, a first switch and a gate driving circuit. The output transistor is connected between the higher potential side power supply line and the output signal line to operate in response to the gate signal on the gate signal line. The first switch is connected to the higher potential side power supply line to turn off in response to the control signal of a first state and turn on in response to the control signal of a second state. The gate driving circuit is connected between the first switch and the control signal line to generate the gate signal onto the gate signal line based on a gate control signal when the first switch is turned on.
Here, the output transistor may be a first N-channel transistor. The output circuit may further include a second switch connected between the gate signal line and the output signal line to turn on in response to the control signal of the first state and to turn off in response to the control signal of t
Nakahara Akihiro
Tamagawa Akio
NEC Electronics Corporation
Tran Toan
Young & Thompson
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