Output circuit for semiconductor device, semiconductor...

Electricity: measuring and testing – Impedance – admittance or other quantities representative of... – Calibration

Reexamination Certificate

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C324S765010

Reexamination Certificate

active

07495453

ABSTRACT:
To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

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Japanese Office Action, with English translation, issued in Japanese Patent Application No. JP 2005-011272, mailed Dec. 4, 2007.

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