Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Patent
1993-05-07
1995-07-11
Hjerpe, Richard
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
345 99, G09G 336
Patent
active
054325293
ABSTRACT:
An output circuit used in a common driver for a flat panel electronic display device includes "n" two-input OR circuits of a CMOS circuit structure, where "n" is a positive integer corresponding to the number of a row electrodes of a flat panel display. One input of each of the OR circuits is connected to a corresponding bit of an n-bit shifter register, and an output of the OR circuits is connected to a corresponding one of the row electrodes of the flat panel display so as to drive the corresponding electrode. A control signal is connected directly to the other input of the first OR circuit and a first one of "n-1" cascaded non-inverting buffers. Outputs of these cascaded non-inverting buffers are connected to the other input of the remaining OR circuits, respectively.
REFERENCES:
patent: 4748444 (1988-05-01), Arai
patent: 5194853 (1993-03-01), Asada
Chang Vivian W.
Hjerpe Richard
NEC Corporation
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