Output circuit for driving a memory device output lead including

Details Output circuit for driving a memory device output lead including Output circuit for driving a memory device output lead including

1988-08-11

1990-07-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307452, 307480, H03K 1900, H03K 19096

Patent

active

049393928

ABSTRACT:
A novel circuit is coupled to a memory device sense amplifier and a memory device output pin for driving the output pin with data. The circuit includes a first inverter (18) and a second inverter (100) coupled to the first inverter. Transfer gates (30, 104) are coupled across the input and output leads of the first and second inverters, respectively. During a first mode of operation, the first and second transfer gates are closed and the second inverter is three-stated so that the input and output leads of the first and second inverters are held at a voltage between VCC and ground. When it is desired to drive the memory device output pin with data, the first and second transfer gates open, and the second inverter leaves the three-state mode and goes into a low output impedance mode. Because the input and output leads of the first and second inverters are held at a voltage between VCC and ground when the transfer gates are closed, when the transfer gates open, the delay between the time the transfer gates open and the time valid output data appears on the output lead of the second inverter is minimized. The second inverter comprises large transistors and can therefore provide a large output current. However, because the second inverter is three-stated when the second transfer gate is closed, the circuit draws minimal power when the first and second transfer gates are closed.

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Wada, et al., "A 34-ns 1-Mbit CMOS SRAM Using Triple Polysilicon", IEEE Journal of Solid State Circuits, Oct., 1987.
Komatsu, et al., "A 35-ns 128K.times.8 CMOS SRAM", IEEE Journal of Solid State Circuits, Oct., 1987.
Ali, et al., "A 50-ns 256K CMOS Split-Gate EPROM", IEEE Journal of Solid State Circuits, Feb., 1988.

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