Output circuit for a programmable logic array

Details Output circuit for a programmable logic array Output circuit for a programmable logic array

1985-03-22

1987-08-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

364716, 34082587, 34082583, H03K 1920, H04A 900

Patent

active

046848304

ABSTRACT:
An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

REFERENCES:
patent: 4051352 (1977-09-01), Eichelberger et al.
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4177452 (1979-12-01), Balasubramanian et al.
patent: 4415818 (1983-11-01), Ogawa et al.
patent: 4422072 (1983-12-01), Cavlan
patent: 4458163 (1984-07-01), Wheeler et al.
"The PAL20RA10 Story-The Customization of a Standard Product" by Marc Baker et al., IEEE Micro, Oct. 1986, pp. 45-60.
PAL Programmable Array Logic Handbook, Third Edition, 1983, Monolithic Memories, Inc.
AmPAL22V10, Preliminary Data Sheet, published by AMD, May, 1984.

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