Output circuit for a programmable logic array

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307243, 328105, H03K 19173, G06F 738

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active

049335774

ABSTRACT:
An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

REFERENCES:
patent: 4422072 (1983-12-01), Cavlan
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4684830 (1987-08-01), Tsui et al.
patent: 4717912 (1988-01-01), Harvey et al.
Programmable Array Logic PAL20RA10, Monolithic Memories Inc. data manual, 1985.
AMPAL 22V10 Advanced Micro Devices, Inc., 1984.
"The PAL 20RA10 Story-the Customization of a Standard Product," Baker et al., IEEE Micro, Oct. 1986, pp. 45-60.

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