Output circuit and method for reducing simultaneous...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S161000, C327S251000, C326S085000, C326S087000

Reexamination Certificate

active

06847238

ABSTRACT:
An output circuit for outputting data with reduced simultaneous switching output skew includes N counts of output buffers and a comparator. The N counts of output buffers receive N counts of bit signals, respectively. At least one of the output buffers includes a delay unit for processing one of the bit signals into a delayed bit signal with an adjustable delay period in response to a delay signal, a pull-up unit electrically connected to the delay unit and a source voltage, and selectively enabled to output the delayed bit signal as a high level, and a pull-down unit electrically connected to the delay unit and a ground voltage, and selectively enabled to output the delayed bit signal as a low level. The comparator is electrically connected to the N counts of output buffers, compares the N counts of bit signals sampled at a first time spot and a second time spot, and generates the delay signal according to the comparing result.

REFERENCES:
patent: 6002601 (1999-12-01), Pappalardo et al.
patent: 6046624 (2000-04-01), Nam et al.
patent: 6166562 (2000-12-01), Mita et al.
patent: 6700403 (2004-03-01), Dillon

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