Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Patent
1997-03-07
2000-01-25
Nuton, My-Trang
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
327374, H03K 300, H03B 100
Patent
active
060182563
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an output circuit for a semiconductor device, and in particular to an output circuit providing high-speed data output and low noise characteristics, and also relates to an electronic apparatus using the same.
BACKGROUND OF ART
In recent years, with the increasingly fine structure of semiconductor devices, there has been a trend for the power supply voltage driving the devices to be reduced. For this reason, the access time increases in proportion to the reduced power supply voltage, whereas for this kind of device an increase in speed together with the reduced voltage is desirable.
At the same time, as with semiconductor devices of a multi-bit construction, when there is an output circuit formed from transistors which have a large current drive ability (referred to hereinafter as "ability") with respect to an external circuit, then noise can be caused by the parasitic resistance or inductance on the power supply lines or ground lines, and this can lead to malfunctions such as the erroneous writing of data or stray oscillation.
As a means of solving these problems is known a circuit which preceding the data output sets the output lines to an intermediate potential, or the so-called intermediate potential setting circuit (referred to hereinafter as "presetting circuit"). As examples of this type of circuit may be cited, for example, Japanese Patent Application Laid-Open No. 63-112893, Japanese Patent Application Laid-Open No. 63-117839, Japanese Patent Application Laid-Open No. 8-77775 (referred to hereinafter as "the first type"), and Japanese Patent Application Laid-Open No. 2-113493, Japanese Patent Application Laid-Open No. 1-149290 (referred to hereinafter as "the second type").
In particular the structure of the first type as disclosed in Japanese Patent Application Laid-Open No. 63-112893 (referred to hereinafter as "prior art 1") is shown in FIG. 23A, an equivalent circuit for preset operation is shown in FIG. 23B, and operating waveforms thereof are shown in FIGS. 24A and 24B. It should be noted that FIG. 24A shows the case where the output capacitance C.sub.L is a low load capacitance, at approximately 30 pF, and FIG. 24B shows the case where the output capacitance C.sub.L is a high load capacitance, at 100 pF or more.
In this device, by means of a presetting circuit 200 an output terminal D.sub.out is set to an intermediate potential determined by the ability ratio of Nch transistor Q2a and Pch transistor Q1a. For example, if output terminal D.sub.out is initially high, the Pch transistor Q1a conducts, and the drain voltage DN rises, and consequently the potential of the output terminal D.sub.out falls as a result of the current I.sub.on2 and the current I.sub.on, thus being preset.
However, there are the following problems with a device of the above type.
(1) During the presetting, Pch transistors Q1a and Q6a, and Nch transistors Q2a and Q12a are all switched on, so that through currents I.sub.op2 and I.sub.on2 are generated, and the power consumption is increased. In particular this is a problem with a high voltage power supply.
(2) Again, with regard to I.sub.on2, in a multi-bit output configuration, during presetting the amount of current flowing in the internal circuits increases substantially, and this leads to problems such as the generation of noise and faulty operation in peripheral circuits.
In more detail, during the presetting, as shown in FIGS. 24A and FIG. 24B, the current I.sub.on2 becomes larger than the current I.sub.on. Here the current I.sub.on2 flows when the output terminal D.sub.out is at a potential above the threshold voltage of the Pch transistor Q1a including a voltage due to the substrate bias effect. The current I.sub.on flows when the output terminal D.sub.out is at a potential above the sum of the threshold voltage of the Nch transistor Q4a and the threshold voltage of the Pch transistor Q1a including a voltage due to the substrate bias effect.
Moreover, in a semiconductor device with a large output buffer, to preve
REFERENCES:
patent: 4983860 (1991-01-01), Yim et al.
patent: 5546029 (1996-08-01), Koke
Kumagai Takashi
Tokuda Yasunobu
Nuton My-Trang
Seiko Epson Corporation
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