Output buffer with slew-rate enhancement output stage

Details Output buffer with slew-rate enhancement output stage Output buffer with slew-rate enhancement output stage

2011-06-28

2011-06-28

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

C327S108000

Reexamination Certificate

active

07969217

ABSTRACT:
An embodiment of a slew-rate enhancement output stage is disclosed. A first slew-rate enhancement circuit receives a first control voltage and outputs a first voltage. A second slew-rate enhancement circuit receives a second control voltage and outputs a second voltage. A first PMOS transistor includes a first first terminal coupled to a high voltage source, a first control terminal receiving the first voltage, and a first second terminal coupled to a voltage output terminal. A first NMOS transistor includes a second first terminal coupled to the voltage output terminal, a second control terminal for receiving the second voltage, and a second second terminal coupled to a low voltage source. The first voltage is higher than the first control voltage, and the second voltage is lower than the second control voltage.

REFERENCES:
patent: 5623216 (1997-04-01), Penza et al.
patent: 5850159 (1998-12-01), Chow et al.
patent: 6535020 (2003-03-01), Yin
patent: 6646483 (2003-11-01), Shin
patent: 6992511 (2006-01-01), Suzuki
patent: 7728641 (2010-06-01), Lee

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