Output buffer with selectable slew rate

Details Output buffer with selectable slew rate Output buffer with selectable slew rate

2007-01-30

2007-01-30

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Slope control of leading or trailing edge of rectangular or...

C327S171000, C327S108000, C327S112000, C326S082000, C326S083000

Reexamination Certificate

active

10891048

ABSTRACT:
A buffer design for an integrated circuit that has adjustable slew rate control, yet requires significantly less space to fabricate than does a conventional buffer with slew rate control. A new slew rate control circuit design is added to a Complementary Metal Oxide Semiconductor CMOS buffer to implement slew rate control in the buffer (e.g., selection between a high slew rate and a low slew rate). The new slew rate control circuit requires significantly less space to fabricate, and when applied to each buffer in an given integrated circuit, e.g., input/output buffers that may be placed along the periphery of the integrated circuit, the savings can be extraordinary.

REFERENCES:
patent: 5216293 (1993-06-01), Sei et al.
patent: 5239440 (1993-08-01), Merrill
patent: 5345357 (1994-09-01), Pianka
patent: 5568081 (1996-10-01), Lui et al.
patent: 5926651 (1999-07-01), Johnston et al.
patent: 6617891 (2003-09-01), Srikanth et al.
patent: 6653873 (2003-11-01), Nguyen

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