Output buffer with improved ESD protection

Details Output buffer with improved ESD protection Output buffer with improved ESD protection

1987-11-18

1989-08-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307450, 307550, 307568, 307443, 357 2313, 361 91, H03K 500, H02H 324

Patent

active

048556203

ABSTRACT:
An output buffer having improved ESD tolerance is disclosed. The output buffer according to the invention incorporates a field oxide, or other high threshold voltage transistor, having its source-to-drain path connected between ground and the gate of the pull-down transistor, and has its gate connected to the output terminal. The threshold voltage of the high threshold device is greater than the power supply voltage, so as not to turn on during normal operation, but is lower than the BV.sub.CBO of the parasitic bipolar transistor associated with the pull-down transistor. The high threshold voltage device turns on with a positive voltage above its threshold appearing at the output terminal, such as occurs in an ESD event, resulting in the gate of the pull-down transistor being biased to ground. This causes the bipolar conduction, and the associated localized J-E heating, to take place away from the surface of the semiconductor, and away from the metal or silicide layers which provide the source of material for melt filaments. A similar high threshold transistor may be provided for biasing the gate of a pull-up transistor to the power supply terminal, having the same effect in the event of an ESD pulse positive relative to the power supply terminal. The high threshold transistors may be constructed as field oxide transistors, and preferably have large channel width-to-length ratios for fast switching.

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Duvvury et al., "ESD Phenomena and Protection Issues in CMOS Output Buffers," Proceedings of the IRPS (IEEE, 1987).
Duvvury et al., "ESD Protection Reliability in 1 .mu.m CMOS Technologies," Proceedings of the IRPS (IEEE, 1986).

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