Output buffer with controlled output level

Details Output buffer with controlled output level Output buffer with controlled output level

1992-02-18

1993-09-28

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307263, H03K 1716

Patent

active

052489078

ABSTRACT:
An output buffer with a controlled high logic state prevents the output voltage from increasing when the supply voltage, Vcc, increases. A fast low-to-high logic transition is achieved by using a pumping circuit to improve the low-to-high transition rate. However, when the Vcc voltage rises past a threshold value, the pumping circuit will only be enabled during a portion of the transition time. This prevents the output level from increasing beyond its nominal value. Because the output voltage is controlled, the high-to-low transition time is reduced and the ground bounce or noise generated by the output signal is minimized.

REFERENCES:
patent: 4543494 (1985-09-01), Wakimoto
patent: 4659944 (1987-04-01), Miller
patent: 4678950 (1987-07-01), Mitake
patent: 4808839 (1989-02-01), Dunn et al.
patent: 4894561 (1990-01-01), Nogami
patent: 5017803 (1991-05-01), Yoshido
patent: 5019720 (1991-05-01), Skoog
patent: 5036222 (1991-07-01), Davis
patent: 5066873 (1991-11-01), Chan et al.
patent: 5138194 (1992-08-01), Yoeli

Affiliated with

Also associated with

Rating

Output buffer with controlled output level does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer with controlled output level, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer with controlled output level will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2192843