Output buffer with charge-pumped noise cancellation

Details Output buffer with charge-pumped noise cancellation Output buffer with charge-pumped noise cancellation

2000-09-28

2002-05-14

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

C327S390000, C327S551000, C327S380000

Reexamination Certificate

active

06388503

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to reducing input/output (I/O) noise in integrated circuits (ICs), and more particularly to implementing a charge-pump synchronization noise cancellation method and apparatus.
2. Background Information
Traditional digital CMOS (complementary metal oxide semiconductor) or GTL (Gunning transceiver logic) I/O buffers cause considerable power supply noise upon switching by generating substantial delta current/delta time (di/dt) transients. Package inductance causes common mode noise on the common voltage (Vcc) and source voltage (Vss) lines. At the same time, a finite amount of low-pass filter capacitance from Vcc to Vss causes differential mode noise on the on-chip power supply by affecting noise margins. Process scaling and bus speed increases have led to a situation where large amounts of silicon area at each I/O slice are used for passive decoupling capacitors that are typically required to reduce noise. The additional area required for decoupling capacitors may take as much as half or more of the allocated area.
FIG. 1
illustrates a basic GTL circuit
100
having its output coupled to a 50 ohm bus terminated at both ends. On-chip decoupling capacitor
110
, package inductance
120
and
122
, and I/O pad
130
are also shown. The output circuit could be other types of circuits, such as CMOS (complementary metal oxide semiconductor), but GTL was chosen in order to simplify this example.
Noise occurs when the output switches from high to low or from low to high.
FIG. 2
shows the path that current
210
from the external supply takes when the output transitions from high to low. Current will ramp up in the inductance
122
to external Vss because of di/dt, causing a voltage drop to external Vss as well as a dip in the on-chip Vcc-to-Vss voltage. At worst, noise will occur when all outputs of a GTL bus switch at once.
Another method to reduce output noise is as follows. For every data bit transmitted, one can transmit a redundant complementary bit as well. Thus, doubling the output circuit area, power and number of external connections. This also assures low noise because of a steady current requirement. Other methods, such as coding, assure that extreme cases of large numbers of I/Os flipping from 1 to 0 or 0 to 1 do not occur.


REFERENCES:
patent: 5736888 (1998-04-01), Sharpe-Geisler
patent: 5789964 (1998-08-01), Voldman
patent: 6191647 (2001-02-01), Tanaka et al.

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